orangecrab: remove dm_remapping workaround: we are now using Wihsbone/L2 path with VexRiscv-SMP on this board.
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@ -183,8 +183,7 @@ class BaseSoC(SoCCore):
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self.submodules.ddrphy = ECP5DDRPHY(
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self.submodules.ddrphy = ECP5DDRPHY(
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pads = ddram_pads,
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pads = ddram_pads,
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sys_clk_freq = sys_clk_freq,
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sys_clk_freq = sys_clk_freq,
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cmd_delay = 0 if sys_clk_freq > 64e6 else 100,
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cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
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dm_remapping = {0:1, 1:0})
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self.ddrphy.settings.rtt_nom = "disabled"
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self.ddrphy.settings.rtt_nom = "disabled"
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self.add_csr("ddrphy")
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self.add_csr("ddrphy")
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if hasattr(ddram_pads, "vccio"):
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if hasattr(ddram_pads, "vccio"):
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