platforms: make sure all plarforms have separators.

litex_boards/platforms/de10lite.py

@@ -5,6 +5,7 @@ from litex.build.generic_platform import *
 from litex.build.altera import AlteraPlatform
 from litex.build.altera.programmer import USBBlaster
 
+# IOs ----------------------------------------------------------------------------------------------
 
 _io = [
     ("clk10", 0, Pins("N5"),  IOStandard("3.3-V LVTTL")),
@@ -103,6 +104,7 @@ _io = [
     )
 ]
 
+# Platform -----------------------------------------------------------------------------------------
 
 class Platform(AlteraPlatform):
     default_clk_name   = "clk50"

litex_boards/platforms/de1soc.py

@@ -5,7 +5,7 @@ from litex.build.generic_platform import *
 from litex.build.altera import AlteraPlatform
 from litex.build.altera.programmer import USBBlaster
 
-# IOs ------------------------------------------------------------------
+# IOs ----------------------------------------------------------------------------------------------
 
 _io = [
     ("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
@@ -34,7 +34,7 @@ _io = [
     ),
 ]
 
-# Platform -------------------------------------------------------------
+# Platform -----------------------------------------------------------------------------------------
 
 class Platform(AlteraPlatform):
     default_clk_name   = "clk50"

litex_boards/platforms/de2_115.py

@@ -5,7 +5,7 @@ from litex.build.generic_platform import *
 from litex.build.altera import AlteraPlatform
 from litex.build.altera.programmer import USBBlaster
 
-# IOs ------------------------------------------------------------------
+# IOs ----------------------------------------------------------------------------------------------
 
 _io = [
     ("clk50", 0, Pins("Y2"), IOStandard("3.3-V LVTTL")),
@@ -34,7 +34,7 @@ _io = [
     ),
 ]
 
-# Platform -------------------------------------------------------------
+# Platform -----------------------------------------------------------------------------------------
 
 class Platform(AlteraPlatform):
     default_clk_name   = "clk50"

litex_boards/platforms/nereid.py

@@ -165,6 +165,8 @@ _io = [
     ),
 ]
 
+# Connectors ---------------------------------------------------------------------------------------
+
 _connectors = [
     ("HPC", {
 

litex_boards/platforms/sp605.py

@@ -1,11 +1,12 @@
 # This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
 # License: BSD
 
-
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform
 from litex.build.openocd import OpenOCD
 
+# IOs ----------------------------------------------------------------------------------------------
+
 _io = [
     ("user_led", 0, Pins("D17"), IOStandard("LVCMOS25")),
     ("user_led", 1, Pins("AB4"), IOStandard("LVCMOS25")),
@@ -56,6 +57,8 @@ _io = [
     ),
 ]
 
+# Connectors ---------------------------------------------------------------------------------------
+
 _connectors = [
     ("LPC", {
         "DP0_C2M_P"     : "B16",
@@ -154,6 +157,8 @@ _connectors = [
     }),
 ]
 
+# Platform -----------------------------------------------------------------------------------------
+
 class Platform(XilinxPlatform):
     default_clk_name   = "clk200"
     default_clk_period = 1e9/200e6

litex_boards/platforms/trellisboard.py

@@ -198,6 +198,8 @@ _io = [
     ),
 ]
 
+# Connectors ---------------------------------------------------------------------------------------
+
 _connectors = [
     ("pmoda", "F19 F20 B22 C23 D14 A13 E22 D23"),
     ("pmodb", "C25 A26 F23 F25 B25 D25 F22 F24"),