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adi_adrv2crr_fmc: Speedgrade of the PLL is -2 

Speedgrade of the chip was updated in a previous commit, but
I forgot to update the PLL too

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2024-02-05 11:42:14 +01:00
parent 39dc0b36a4
commit 2264df8a0a
1 changed files with 1 additions and 1 deletions
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2
litex_boards/targets/adi_adrv2crr_fmc.py
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@ -41,7 +41,7 @@ class CRG(LiteXModule):
# # # # # #
self.pll = pll = USPMMCM(speedgrade=-1) self.pll = pll = USPMMCM(speedgrade=-2)
self.comb += pll.reset.eq(self.rst) self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("ddram_refclk", ddram_channel), 300e6) pll.register_clkin(platform.request("ddram_refclk", ddram_channel), 300e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)