Merge pull request #47 from antmicro/zcu104
Add support for ZCU104 board
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enjoy-digital
GitHub
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22b0449509
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk125", 0,
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Subsignal("p", Pins("F23"), IOStandard("LVDS")),
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Subsignal("n", Pins("E23"), IOStandard("LVDS")),
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),
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("clk300", 0,
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Subsignal("p", Pins("AH18"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("n", Pins("AH17"), IOStandard("DIFF_SSTL12_DCI")),
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),
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("user_led", 0, Pins("D5"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D6"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("A5"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("B5"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("M11"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("B4"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("C4"), IOStandard("LVCMOS33")),
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("user_btn", 2, Pins("B3"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("C3"), IOStandard("LVCMOS33")),
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("user_dip", 0, Pins("E4"), IOStandard("LVCMOS33")),
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("user_dip", 1, Pins("D4"), IOStandard("LVCMOS33")),
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("user_dip", 2, Pins("F5"), IOStandard("LVCMOS33")),
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("user_dip", 3, Pins("F4"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("cts", Pins("A19")),
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Subsignal("rts", Pins("C18")),
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Subsignal("tx", Pins("C19")),
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Subsignal("rx", Pins("A20")),
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IOStandard("LVCMOS18")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"AH16 AG14 AG15 AF15 AF16 AJ14 AH14 AF17",
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"AK17 AJ17 AK14 AK15 AL18 AK18"),
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IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("AL15 AL16"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("AC16 AB16"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("AD15"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("cas_n", Pins("AA14"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("we_n", Pins("AA16"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cs_n", Pins("AA15"), IOStandard("SSTL12_DCI")), # also AL17 AN17 AN16 for larger SODIMMs
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Subsignal("act_n", Pins("AC17"), IOStandard("SSTL12_DCI")),
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#Subsignal("alert_n", Pins("AB15"), IOStandard("SSTL12_DCI")),
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#Subsignal("par", Pins("AD16"), IOStandard("SSTL12_DCI")),
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#FIXME: Use full bus width
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#Subsignal("dm", Pins("AH22 AE18 AL20 AP19 AF11 AH12 AK13 AN12"),
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Subsignal("dm", Pins("AF11 AH12 AK13 AN12"),
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IOStandard("POD12_DCI")),
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Subsignal("dq", Pins(
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# "AE24 AE23 AF22 AF21 AG20 AG19 AH21 AG21",
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# "AA20 AA19 AD19 AC18 AE20 AD20 AC19 AB19",
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# "AJ22 AJ21 AK20 AJ20 AK19 AJ19 AL23 AL22",
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# "AN23 AM23 AP23 AN22 AP22 AP21 AN19 AM19",
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"AC13 AB13 AF12 AE12 AF13 AE13 AE14 AD14",
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"AG8 AF8 AG10 AG11 AH13 AG13 AJ11 AH11",
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"AK9 AJ9 AK10 AJ10 AL12 AK12 AL10 AL11",
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"AM8 AM9 AM10 AM11 AP11 AN11 AP9 AP10"
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),
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IOStandard("POD12_DCI")),
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#Subsignal("dqs_p", Pins("AF23 AA18 AK22 AM21 AC12 AG9 AK8 AN9"),
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# IOStandard("DIFF_POD12_DCI")),
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Subsignal("dqs_p", Pins("AC12 AG9 AK8 AN9"),
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IOStandard("DIFF_POD12_DCI")),
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#Subsignal("dqs_n", Pins("AG23 AB18 AK23 AN21 AD12 AH9 AL8 AN8"),
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# IOStandard("DIFF_POD12_DCI")),
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Subsignal("dqs_n", Pins("AD12 AH9 AL8 AN8"),
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IOStandard("DIFF_POD12_DCI")),
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Subsignal("clk_p", Pins("AF18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ16 for larger SODIMMs
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Subsignal("clk_n", Pins("AG18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ15 for larger SODIMMs
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Subsignal("cke", Pins("AD17"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
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Subsignal("odt", Pins("AE15"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
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Subsignal("reset_n", Pins("AB14"), IOStandard("LVCMOS12")),
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Misc("SLEW=FAST"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 65]")
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self.add_platform_command("set_property INTERNAL_VREF {{0.84}} [get_iobanks 66]")
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@ -0,0 +1,110 @@
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#!/usr/bin/env python3
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import argparse
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from migen import *
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from migen.genlib.io import CRG
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from litex_boards.platforms import zcu104
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import KVR21SE15S84
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from litedram.phy import usddrphy
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk500 = ClockDomain()
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self.clock_domains.cd_ic = ClockDomain()
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk500, 500e6, with_reset=False)
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self.specials += [
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Instance("BUFGCE_DIV", name="main_bufgce_div",
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p_BUFGCE_DIVIDE=4,
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
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Instance("BUFGCE", name="main_bufgce",
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i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
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AsyncResetSynchronizer(self.cd_clk500, ~pll.locked),
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]
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ic_reset_counter = Signal(max=64, reset=63)
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ic_reset = Signal(reset=1)
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self.sync.clk500 += \
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If(ic_reset_counter != 0,
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ic_reset_counter.eq(ic_reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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ic_rdy = Signal()
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ic_rdy_counter = Signal(max=64, reset=63)
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self.cd_sys.rst.reset = 1
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self.comb += self.cd_ic.clk.eq(self.cd_sys.clk)
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self.sync.ic += [
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If(ic_rdy,
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If(ic_rdy_counter != 0,
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ic_rdy_counter.eq(ic_rdy_counter - 1)
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).Else(
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self.cd_sys.rst.eq(0)
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)
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)
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]
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self.specials += [
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Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE",
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i_REFCLK=ClockSignal("clk500"), i_RST=ic_reset,
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o_RDY=ic_rdy),
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AsyncResetSynchronizer(self.cd_ic, ic_reset)
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]
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(125e6), **kwargs):
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platform = zcu104.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR4 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"),
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memtype = "DDR4",
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sim_device = "ULTRASCALE_PLUS",
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iodelay_clk_freq = 500e6,
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cmd_latency = 1,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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self.add_constant("USDDRPHY", None)
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sdram_module = KVR21SE15S84(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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