Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

reset is active high

Browse source
This commit is contained in:
Hans Baier 2023-05-08 16:24:15 +07:00
parent 1564ab1eea
commit 22bdb575d1
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex_boards/platforms/pcbarts_klusterlab.py
View file

@ -31,7 +31,7 @@ _io = [
Subsignal("n", Pins("H5"), IOStandard("DIFF_HSTL_I_10"))
),
("cpu_reset_n", 0, Pins("A20"), IOStandard("LVCMOS18")),
("cpu_reset", 0, Pins("A20"), IOStandard("LVCMOS18")),
("pi_reset_n", 0, Pins("A18"), IOStandard("LVCMOS33")),
# Leds

2
litex_boards/targets/pcbarts_klusterlab.py
View file

@ -35,7 +35,7 @@ class _CRG(LiteXModule):
# # #
self.pll = pll = S7PLL(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset_n") | self.rst)
self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst)
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)