Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/sqrl_acorn_cle_215: Add missing false path constraints.

This commit is contained in:
Florent Kermarrec 2021-03-25 18:19:20 +01:00
parent 7d130d6981
commit 22f167dde4
1 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
litex_boards/targets/sqrl_acorn_cle_215.py
View File

@ -107,6 +107,11 @@ class BaseSoC(SoCCore):
data_width = 128,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# FIXME: Improve (Make it generic and apply it to all targets).
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks userclk2] -asynchronous",)
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks clk_125mhz] -asynchronous")
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clkout0] -group [get_clocks clk_250mhz] -asynchronous")
platform.toolchain.pre_placement_commands.append("set_clock_groups -group [get_clocks clk_125mhz] -group [get_clocks clk_250mhz] -asynchronous")
# SATA -------------------------------------------------------------------------------------
if with_sata: