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pano_logic_g2: move gmii_rst_n to _CRG.

This commit is contained in:
Florent Kermarrec 2020-05-26 08:36:06 +02:00
parent 935a71123b
commit 22f18f618e
1 changed files with 4 additions and 6 deletions
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10
litex_boards/targets/pano_logic_g2.py
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@ -24,6 +24,10 @@ class _CRG(Module):
# # # # # #
# Take Ethernet PHY out of reset to enable clk125 (25MHz otherwise).
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += gmii_rst_n.eq(1)
self.submodules.pll = pll = S6PLL(speedgrade=-2) self.submodules.pll = pll = S6PLL(speedgrade=-2)
pll.register_clkin(platform.request("clk125"), 125e6) pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_sys, clk_freq) pll.create_clkout(self.cd_sys, clk_freq)
@ -46,12 +50,6 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds") self.add_csr("leds")
# Take Ethernet Phy out of reset for SYSCLK of 125 Mhz
gmii_rst_n = platform.request("gmii_rst_n")
self.comb += [
gmii_rst_n.eq(1)
]
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():