Merge branch 'master' into crosslink_nx_main_ram

litex_boards/platforms/gsd_orangecrab.py

@@ -229,7 +229,7 @@ class Platform(LatticeECP5Platform):
         LatticeECP5Platform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, toolchain=toolchain, **kwargs)
 
     def create_programmer(self):
-        return DFUProg(vid="1209", pid="5af0")
+        return DFUProg(vid="1209", pid="5af0", alt=0)
 
     def do_finalize(self, fragment):
         LatticeECP5Platform.do_finalize(self, fragment)

litex_boards/targets/lattice_crosslink_nx_evn.py

@@ -21,6 +21,7 @@ from litex.build.generic_platform import *
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
@@ -70,6 +71,8 @@ class BaseSoC(SoCCore):
 
     def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant",
         with_led_chaser = True,
+        with_spi_flash  = False,
+        with_uartbone   = False,
         **kwargs):
         platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain)
 
@@ -97,10 +100,15 @@ class BaseSoC(SoCCore):
                 sys_clk_freq = sys_clk_freq)
 
         # UARTBone ---------------------------------------------------------------------------------
-        debug_uart = False
-        if debug_uart:
+        if with_uartbone:
             self.add_uartbone()
 
+        # SPI Flash --------------------------------------------------------------------------------
+        if with_spi_flash:
+            from litespi.modules import MX25L12833F
+            from litespi.opcodes import SpiNorFlashOpCodes as Codes
+            self.add_spi_flash(mode="4x", clk_freq=100_000, module=MX25L12833F(Codes.READ_4_4_4), with_master=True)
+
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -113,12 +121,16 @@ def main():
     parser.add_target_argument("--programmer",    default="radiant",          help="Programmer (radiant or ecpprog).")
     parser.add_target_argument("--address",       default=0x0,                help="Flash address to program bitstream at.")
     parser.add_target_argument("--prog-target",   default="direct",           help="Programming Target (direct or flash).")
+    parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable SPI Flash (MMAPed).")
+    parser.add_target_argument("--with-uartbone", action="store_true",        help="Add UartBone on 1st serial.")
     args = parser.parse_args()
 
     soc = BaseSoC(
         sys_clk_freq = args.sys_clk_freq,
         device       = args.device,
         toolchain    = args.toolchain,
+        with_spi_flash = args.with_spi_flash,
+        with_uartbone = args.with_uartbone,
         **parser.soc_argdict
     )
     builder = Builder(soc, **parser.builder_argdict)
@@ -128,7 +140,7 @@ def main():
     if args.load:
         prog = soc.platform.create_programmer(args.prog_target, args.programmer)
         if args.programmer == "ecpprog" and args.prog_target == "flash":
-            prog.flash(address=args.address, bitstream=builder.get_bitstream_filename(mode="sram"))
+            prog.flash(args.address, builder.get_bitstream_filename(mode="sram"))
         else:
             prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))