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orangecrab/CRGSDRAM: add missing rst signal (to reset from the SoC).

This commit is contained in:
Florent Kermarrec 2021-01-22 22:55:02 +01:00
parent bee71da774
commit 23760e2eae
1 changed files with 2 additions and 1 deletions
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3
litex_boards/targets/orangecrab.py
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@ -76,6 +76,7 @@ class _CRG(Module):
class _CRGSDRAM(Module): class _CRGSDRAM(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False): def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.rst = Signal()
self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
@ -102,7 +103,7 @@ class _CRGSDRAM(Module):
# PLL # PLL
sys2x_clk_ecsout = Signal() sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | ~rst_n) self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
pll.register_clkin(clk48, 48e6) pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 24e6) pll.create_clkout(self.cd_init, 24e6)