fixed issue with default programmer option
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6768be7f66
commit
25c28d2c03
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@ -195,13 +195,13 @@ class Platform(LatticePlatform):
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connectors = {"1.0": _connectors_r1_0}[revision]
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connectors = {"1.0": _connectors_r1_0}[revision]
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LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs)
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LatticePlatform.__init__(self, f"LFE5UM5G-{device}-8BG381C", io, connectors, toolchain=toolchain, **kwargs)
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def create_programmer(self, load):
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def create_programmer(self, programmer):
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if load == "jtag":
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if programmer == "jtag":
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return OpenOCDJTAGProgrammer("openocd_butterstick.cfg")
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return OpenOCDJTAGProgrammer("openocd_butterstick.cfg")
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elif load == "dfu":
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elif programmer == "dfu":
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return DFUProg(vid="1209", pid="5af1", alt=0)
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return DFUProg(vid="1209", pid="5af1", alt=0)
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else:
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else:
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print("Could not program board. " + load + " is not a valid argument. Please use 'jtag' or 'dfu'.")
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print("Could not program board. " + programmer + " is not a valid argument. Please use 'jtag' or 'dfu'.")
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def do_finalize(self, fragment):
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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LatticePlatform.do_finalize(self, fragment)
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@ -8,7 +8,7 @@
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# SPDX-License-Identifier: BSD-2-Clause
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# Build/Use:
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# ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load (jtag / dfu)
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# ./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load --programmer (jtag / dfu)
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# litex_server --udp
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# litex_server --udp
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# litex_term crossover
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# litex_term crossover
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@ -155,7 +155,8 @@ def main():
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parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick")
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parser = LiteXSoCArgumentParser(description="LiteX SoC on ButterStick")
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target_group = parser.add_argument_group(title="Target options")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", default="jtag", help="Load bitstream (jtag or dfu).")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--programmer", default="jtag", help="Programming interface (jtag or dfu).")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
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target_group.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
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target_group.add_argument("--revision", default="1.0", help="Board Revision (1.0).")
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@ -201,7 +202,7 @@ def main():
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builder.build(**builder_kargs)
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builder.build(**builder_kargs)
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if args.load:
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if args.load:
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prog = soc.platform.create_programmer(args.load)
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prog = soc.platform.create_programmer(args.programmer)
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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if __name__ == "__main__":
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