digilent_pynq_z1: Do minor cosmetic cleanups.
This commit is contained in:
Florent Kermarrec
parent
45cfe2be6b
commit
296c99f065
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@ -35,7 +35,7 @@ _io = [
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("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")),
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("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")),
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#Serial
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# Serial
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("serial", 0,
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Subsignal("tx", Pins("pmoda:0")),
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Subsignal("rx", Pins("pmoda:1")),
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@ -44,9 +44,9 @@ _io = [
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# Audio
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("aud_pwm", 0, Pins("R18"), IOStandard("LVCMOS33")),
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("aud_sd", 0, Pins("T17"), IOStandard("LVCMOS33")),
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("m_clk", 0, Pins("F17"), IOStandard("LVCMOS33")),
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("m_data", 0, Pins("G18"), IOStandard("LVCMOS33")),
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("aud_sd", 0, Pins("T17"), IOStandard("LVCMOS33")),
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("m_clk", 0, Pins("F17"), IOStandard("LVCMOS33")),
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("m_data", 0, Pins("G18"), IOStandard("LVCMOS33")),
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# Chipkit Single Ended Analog Input
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("ck_an_n", 0, Pins("D18"), IOStandard("LVCMOS33")),
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@ -65,16 +65,15 @@ _io = [
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# Chipkit SPI
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("ck_miso", 0, Pins("W15"), IOStandard("LVCMOS33")),
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("ck_mosi", 0, Pins("T12"), IOStandard("LVCMOS33")),
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("ck_sck", 0, Pins("H15"), IOStandard("LVCMOS33")),
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("ck_ss", 0, Pins("F16"), IOStandard("LVCMOS33")),
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("ck_sck", 0, Pins("H15"), IOStandard("LVCMOS33")),
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("ck_ss", 0, Pins("F16"), IOStandard("LVCMOS33")),
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# Chipkit I2C
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("ck_scl", 0, Pins("P16"), IOStandard("LVCMOS33")),
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("ck_sda", 0, Pins("P15"), IOStandard("LVCMOS33")),
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# Crypto SDA
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("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33"))
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("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33")),
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]
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_ps7_io = [
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@ -83,13 +82,13 @@ _ps7_io = [
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("ps7_porb", 0, Pins("C7")),
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("ps7_srstb", 0, Pins("B10")),
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("ps7_mio", 0, Pins(
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"E6 A7 B8 D6 B7 A6 A5 D8",
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"D5 B5 E9 C6 D9 E8 C5 C8",
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" E6 A7 B8 D6 B7 A6 A5 D8",
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" D5 B5 E9 C6 D9 E8 C5 C8",
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"A19 E14 B18 D10 A17 F14 B17 D11",
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"A16 F15 A15 D13 C16 C13 C15 E16",
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"A14 D15 A12 F12 A11 A10 E13 C18"
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"D14 C17 E12 A9 F13 B15 D16 B14"
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"B12 C12 B13 B9 C10 C11")),
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"D14 C17 E12 A9 F13 B15 D16 B14"
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"B12 C12 B13 B9 C10 C11")),
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("ps7_ddram", 0,
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Subsignal("addr", Pins(
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"N2 K2 M3 K3 M4 L1 L4 K4",
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@ -102,10 +101,10 @@ _ps7_io = [
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Subsignal("cs_n", Pins("N1")),
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Subsignal("dm", Pins("A1 F1 T1 Y1")),
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Subsignal("dq", Pins(
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" C3 B3 A2 A4 D3 D1 C1 E1",
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" E2 E3 G3 H3 J3 H2 H1 J1",
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" P1 P3 R3 R1 T4 U4 U2 U3",
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" V1 Y3 W1 Y4 Y2 W3 V2 V3"),
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"C3 B3 A2 A4 D3 D1 C1 E1",
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"E2 E3 G3 H3 J3 H2 H1 J1",
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"P1 P3 R3 R1 T4 U4 U2 U3",
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"V1 Y3 W1 Y4 Y2 W3 V2 V3"),
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),
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Subsignal("dqs_n", Pins("B2 F2 T2 W4")),
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Subsignal("dqs_p", Pins("C2 G2 R2 W5")),
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@ -120,37 +119,37 @@ _ps7_io = [
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_hdmi_rx_io = [
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# HDMI Rx
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("hdmi_rx", 0,
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Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("N18"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")),
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Subsignal("hpd", Pins("T19"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")),
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("hdmi_rx", 0,
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Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("N18"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")),
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Subsignal("hpd", Pins("T19"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")),
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),
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]
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_hdmi_tx_io = [
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# HDMI Tx
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("hdmi_tx", 0,
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Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")),
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Subsignal("hpdn", Pins("R19"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")),
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("hdmi_tx", 0,
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Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")),
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Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")),
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Subsignal("hpdn", Pins("R19"), IOStandard("LVCMOS33")),
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Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")),
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),
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]
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@ -28,16 +28,16 @@ from litex.soc.cores.led import LedChaser
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, toolchain, use_ps7_clk=False, with_video_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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# # #
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# Clk
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# Clk
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clk125 = platform.request("sysclk")
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# PLL
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# PLL
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if use_ps7_clk:
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assert sys_clk_freq == 125e6
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self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
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@ -49,7 +49,7 @@ class _CRG(Module):
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# Video PLL.
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# Video PLL.
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if with_video_pll:
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self.submodules.video_pll = video_pll = S7MMCM(speedgrade=-1)
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video_pll.reset.eq(self.rst)
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@ -89,7 +89,7 @@ class BaseSoC(SoCCore):
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_terminal)
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# Video ------------------------------------------------------------------------------------
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_tx"), clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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@ -104,10 +104,10 @@ class BaseSoC(SoCCore):
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on PYNQ Z1")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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@ -115,9 +115,9 @@ def main():
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**vivado_build_argdict(args), run=args.build)
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