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ac701: add pcie_x1 pins

This commit is contained in:
Florent Kermarrec 2019-11-06 09:29:55 +01:00
parent 5bd8c4d74f
commit 2a0fbcadd2
1 changed files with 10 additions and 0 deletions
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10
litex_boards/community/platforms/ac701.py
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@ -83,6 +83,16 @@ _io = [
Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15")) Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15"))
), ),
("pcie_x1", 0,
Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("F11")),
Subsignal("clk_n", Pins("E11")),
Subsignal("rx_p", Pins("D12")),
Subsignal("rx_n", Pins("C12")),
Subsignal("tx_p", Pins("D10")),
Subsignal("tx_n", Pins("C10"))
),
("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")), ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
("gtp_refclk", 0, ("gtp_refclk", 0,