platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3).

2020-07-18 22:18:41 +02:00 · 2020-07-18 22:18:41 +02:00 · 2ce24df76d
parent 135c387155
commit 2ce24df76d
1 changed files with 1 additions and 0 deletions
--- a/litex_boards/platforms/genesys2.py
+++ b/litex_boards/platforms/genesys2.py
@ -145,6 +145,7 @@ class Platform(XilinxPlatform):

    def __init__(self):
        XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
+        self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")

    def create_programmer(self):
        return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")