targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).

This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
2020-07-26 11:58:42 +02:00 · 2020-07-26 11:58:42 +02:00 · 2cef54a909
parent bfbee484c7
commit 2cef54a909
1 changed files with 0 additions and 3 deletions
--- a/litex_boards/targets/colorlight_5a_75x.py
+++ b/litex_boards/targets/colorlight_5a_75x.py
@ -103,9 +103,6 @@ class BaseSoC(SoCCore):
        elif board == "5a-75e":
            platform = colorlight_5a_75e.Platform(revision=revision)

-        if with_etherbone:
-            sys_clk_freq = int(125e6)
-
        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on Colorlight " + board.upper(),