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antmicro_lpddr4_test_board: fix ethernet rx delay issue

This commit is contained in:
Jędrzej Boczar 2021-04-23 15:25:47 +02:00
parent 228a9650d4
commit 2d2a10621f
1 changed files with 6 additions and 1 deletions
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7
litex_boards/targets/antmicro_lpddr4_test_board.py
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@ -91,9 +91,14 @@ class BaseSoC(SoCCore):
# Ethernet / Etherbone --------------------------------------------------------------------- # Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone: if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII( self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads = self.platform.request("eth_clocks"), clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth")) pads = self.platform.request("eth"),
rx_delay = 0.8e-9,
)
if with_ethernet: if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone: if with_etherbone: