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quicklogic_quickfeather: Update clocking.

This commit is contained in:
Florent Kermarrec 2021-11-14 09:19:19 +01:00
parent df468fcf85
commit 2d3422869c
1 changed files with 2 additions and 2 deletions
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4
litex_boards/targets/quicklogic_quickfeather.py
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@ -32,8 +32,8 @@ class _CRG(Module):
class Open(Signal): pass
if is_eoss3_cpu:
self.comb += ClockSignal("sys").eq(ClockSignal("Sys_Clk0"))
self.comb += ResetSignal("sys").eq(ResetSignal("Sys_Clk0") | self.rst)
self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0"))
self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst)
else:
self.specials += Instance("qlal4s3b_cell_macro",
o_Sys_Clk0 = self.cd_sys.clk,