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litex-boards
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targets/simple: simplify (only keep minimal SoC + Leds) and add load argument. 

ex of use:
./simple.py litex_boards.platform.ulx3s --build --load
./simple.py litex_boards.platform.trellisboard --build --load
./simple.py litex_boards.platform.arty --build --load
etc...
This commit is contained in:
Florent Kermarrec 2020-11-12 13:34:43 +01:00
parent a4d05522d4
commit 302e4ffdff
1 changed files with 15 additions and 15 deletions
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30
litex_boards/targets/simple.py
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@ -3,7 +3,7 @@
# #
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
# Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk> # Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
@ -18,7 +18,7 @@ from litex.build.io import CRG
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from liteeth.phy import LiteEthPHY from litex.soc.cores.led import LedChaser
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
@ -35,14 +35,11 @@ class BaseSoC(SoCCore):
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name)) self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Ethernet --------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_ethernet: self.submodules.leds = LedChaser(
self.submodules.ethphy = LiteEthPHY( pads = platform.request_all("user_led"),
clock_pads = self.platform.request("eth_clocks"), sys_clk_freq = sys_clk_freq)
pads = self.platform.request("eth"), self.add_csr("leds")
clk_freq = self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
@ -50,21 +47,24 @@ def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC") parser = argparse.ArgumentParser(description="Generic LiteX SoC")
parser.add_argument("platform", help="Module name of the platform to build for") parser.add_argument("platform", help="Module name of the platform to build for")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default=None, help="FPGA toolchain (None default)") parser.add_argument("--toolchain", default=None, help="FPGA toolchain (None default)")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
platform_module = importlib.import_module(args.platform) platform_module = importlib.import_module(args.platform)
platform_kwargs = {}
if args.toolchain is not None: if args.toolchain is not None:
platform = platform_module.Platform(toolchain=args.toolchain) platform_kwargs["toolchain"] = args.toolchain
else: platform = platform_module.Platform(**platform_kwargs)
platform = platform_module.Platform() soc = BaseSoC(platform,**soc_core_argdict(args))
soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + platform.bitstream_ext))
if __name__ == "__main__": if __name__ == "__main__":
main() main()