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targets: keep attributes are no longer needed since automatically added when applying constraints to signals.

This commit is contained in:
Florent Kermarrec 2019-12-06 16:01:53 +01:00
parent 8fa3f09226
commit 30ea463b41
14 changed files with 0 additions and 68 deletions
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6
litex_boards/community/targets/ac701.py
View File

@ -34,10 +34,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk200"), 200e6)
@ -92,8 +88,6 @@ class EthernetSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(

4
litex_boards/community/targets/de10lite.py
View File

@ -25,10 +25,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)

4
litex_boards/community/targets/de1soc.py
View File

@ -25,10 +25,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)

4
litex_boards/community/targets/de2_115.py
View File

@ -25,10 +25,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)

2
litex_boards/community/targets/ecp5_evn.py
View File

@ -22,8 +22,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
# clk / rst
clk = clk12 = platform.request("clk12")
rst_n = platform.request("rst_n")

6
litex_boards/official/targets/arty.py
View File

@ -32,10 +32,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
@ -97,8 +93,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints(

4
litex_boards/official/targets/de0nano.py
View File

@ -25,10 +25,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
# Power on reset
rst_n = Signal()
self.sync.por += rst_n.eq(1)

5
litex_boards/official/targets/genesys2.py
View File

@ -29,9 +29,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
pll.register_clkin(platform.request("clk200"), 200e6)
@ -87,8 +84,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(

5
litex_boards/official/targets/kc705.py
View File

@ -31,9 +31,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk200"), 200e6)
@ -91,8 +88,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(

5
litex_boards/official/targets/kcu105.py
View File

@ -30,9 +30,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(platform.request("cpu_reset"))
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
@ -127,8 +124,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.cd_eth_rx.clk.attr.add("keep")
self.ethphy.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(

3
litex_boards/official/targets/minispartan6.py
View File

@ -29,9 +29,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys_ps.clk.attr.add("keep")
self.submodules.pll = pll = S6PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk32"), 32e6)
pll.create_clkout(self.cd_sys, clk_freq)

6
litex_boards/official/targets/nexys4ddr.py
View File

@ -31,10 +31,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
@ -95,8 +91,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
self.platform.add_false_path_constraints(

6
litex_boards/official/targets/nexys_video.py
View File

@ -31,10 +31,6 @@ class _CRG(Module):
# # #
self.cd_sys.clk.attr.add("keep")
self.cd_sys4x.clk.attr.add("keep")
self.cd_sys4x_dqs.clk.attr.add("keep")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(

8
litex_boards/official/targets/versa_ecp5.py
View File

@ -35,12 +35,6 @@ class _CRG(Module):
# # #
self.cd_init.clk.attr.add("keep")
self.cd_por.clk.attr.add("keep")
self.cd_sys.clk.attr.add("keep")
self.cd_sys2x.clk.attr.add("keep")
self.cd_sys2x_i.clk.attr.add("keep")
self.stop = Signal()
# clk / rst
@ -124,8 +118,6 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)