Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Updated copywrite and renamed to avnet_aesku40

This commit is contained in:
AEW2015 2022-06-03 20:49:52 -06:00
parent 4d98dd38a7
commit 313e758ffe
3 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
README.md
View File

@ -105,6 +105,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try!
├── antmicro_lpddr4_test_board ├── antmicro_lpddr4_test_board
├── arduino_mkrvidor4000 ├── arduino_mkrvidor4000
├── avalanche ├── avalanche
├── avnet_aesku40
├── berkeleylab_marblemini ├── berkeleylab_marblemini
├── berkeleylab_marble ├── berkeleylab_marble
├── camlink_4k ├── camlink_4k

2
litex_boards/platforms/xilinx_aesku40.py → litex_boards/platforms/avnet_aesku40.py
View File

@ -1,7 +1,7 @@
# #
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
# Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2022 Andrew Elbert Wilson <andrew.e.wilson@ieee.org>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import * from litex.build.generic_platform import *

6
litex_boards/targets/xilinx_aesku40.py → litex_boards/targets/avnet_aesku40.py
View File

@ -3,7 +3,7 @@
# #
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
# Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2022 Andrew Elbert Wilson <andrew.e.wilson@ieee.org>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
import os import os
@ -12,7 +12,7 @@ import argparse
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import aesku40 from litex_boards.platforms import avnet_aesku40
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
@ -66,7 +66,7 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False,
eth_ip="192.168.1.50", with_led_chaser=True, with_pcie=False, with_sata=False, eth_ip="192.168.1.50", with_led_chaser=True, with_pcie=False, with_sata=False,
**kwargs): **kwargs):
platform = aesku40.Platform() platform = avnet_aesku40.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,