Merge pull request #122 from baselsayeh/master
add Qmtech EP4CE15 coreboard support
This commit is contained in:
enjoy-digital
GitHub
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31eb74dc2d
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Basel Sayeh <Basel.Sayeh@hotmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.altera import AlteraPlatform
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from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
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# Leds
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("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
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# Button
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("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
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("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
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# Serial
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("serial", 0,
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# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
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Subsignal("tx", Pins("AA13"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
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Subsignal("rx", Pins("AA14"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
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),
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# SDR SDRAM
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("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("a", Pins(
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"V2 V1 U2 U1 V3 V4 Y2 AA1",
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"Y3 V5 W1 Y4 V6")),
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Subsignal("ba", Pins("Y1 W2")),
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Subsignal("cs_n", Pins("AA3")),
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Subsignal("cke", Pins("W6")),
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Subsignal("ras_n", Pins("AB3")),
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Subsignal("cas_n", Pins("AA4")),
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Subsignal("we_n", Pins("AB4")),
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Subsignal("dq", Pins(
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"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
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"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
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Subsignal("dm", Pins("AA5 W7")),
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IOStandard("3.3-V LVTTL")
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),
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# GPIOs
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#ignore for now
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#("gpio_0", 0, Pins(
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# "D3 C3 A2 A3 B3 B4 A4 B5",
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# "A5 D5 B6 A6 B7 D6 A7 C6",
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# "C8 E6 E7 D8 E8 F8 F9 E9",
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# "C9 D9 E11 E10 C11 B11 A12 D11",
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# "D12 B12"),
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# IOStandard("3.3-V LVTTL")
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#),
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#("gpio_1", 0, Pins(
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# "F13 T15 T14 T13 R13 T12 R12 T11",
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# "T10 R11 P11 R10 N12 P9 N9 N11",
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# "L16 K16 R16 L15 P15 P16 R14 N16",
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# "N15 P14 L14 N14 M10 L13 J16 K15",
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# "J13 J14"),
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# IOStandard("3.3-V LVTTL")
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#),
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#("gpio_2", 0, Pins(
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# "A14 B16 C14 C16 C15 D16 D15 D14",
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# "F15 F16 F14 G16 G15"),
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# IOStandard("3.3-V LVTTL")
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#),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self):
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AlteraPlatform.__init__(self, "EP4CE15F23C8", _io)
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def create_programmer(self):
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return USBBlaster()
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,115 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2020 Basel Sayeh <Basel.Sayeh@hotmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from litex_boards.platforms import qmtech_EP4CE15
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from litex.soc.cores.clock import CycloneIVPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import IS42S16160
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
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platform = qmtech_EP4CE15.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on qmtech_EP4CE15",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = IS42S16160(sys_clk_freq, sdram_rate),
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origin = self.mem_map["main_ram"],
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size = kwargs.get("max_sdram_size", 0x40000000),
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l2_cache_size = kwargs.get("l2_size", 8192),
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l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
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l2_cache_reverse = True
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)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on qmtech_EP4CE15")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
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builder_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
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if __name__ == "__main__":
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main()
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