[init] added colorlight i9+ based on XC7A50 FPGA
This commit is contained in:
Charles-Henri Mousset
parent
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commit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk25", 0, Pins("K4"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("A18"), IOStandard("LVCMOS33")),
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# RGMII Ethernet (B50612D)
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("eth_clocks", 0, # U5 is SDIO phy #0
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Subsignal("tx", Pins("A1")),
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Subsignal("rx", Pins("H4")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("H2")),
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Subsignal("mdio", Pins("G2")),
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Subsignal("mdc", Pins("G1")),
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Subsignal("rx_ctl", Pins("F1")),
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Subsignal("rx_data", Pins("E3 E2 E1 F3")),
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Subsignal("tx_ctl", Pins("D1")),
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Subsignal("tx_data", Pins("B2 B1 C2 D2")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1, # U9 is SDIO phy #1
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Subsignal("tx", Pins("M6")),
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Subsignal("rx", Pins("L3")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rst_n", Pins("H2")),
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Subsignal("mdio", Pins("G2")),
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Subsignal("mdc", Pins("G1")),
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Subsignal("rx_ctl", Pins("R1")),
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Subsignal("rx_data", Pins("N2 N3 P1 P2")),
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Subsignal("tx_ctl", Pins("N5")),
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Subsignal("tx_data", Pins("M5 M2 N4 P4")),
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IOStandard("LVCMOS33")
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),
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# M12L64322A
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("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"C20 C19 C13 F13 G13 G15 "
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"F14 F18 E13 E18 C14 A13")), # address pin A11 routed but NC on M12L64322A
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Subsignal("dq", Pins(
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"F21 E22 F20 E21 F19 D22 E19 D21 "
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"K21 L21 K22 M21 L20 M22 N20 M20 "
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"B18 D20 A19 A21 A20 B21 C22 B22 "
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"G21 G22 H20 H22 J20 J22 G20 J21 "
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)),
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Subsignal("we_n", Pins("D17")),
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Subsignal("ras_n", Pins("A14")),
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Subsignal("cas_n", Pins("D14")),
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#Subsignal("cs_n", Pins("")), # gnd
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#Subsignal("cke", Pins("")), # 3v3
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Subsignal("ba", Pins("D19 B13")),
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#Subsignal("dm", Pins("")), # gnd
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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("dimm",
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"- "
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"GND 5V GND 5V GND 5V GND 5V GND 5V " # 1-10
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"GND 5V NC NC ETH1_1P ETH2_1P ETH1_1N ETH2_1N NC NC " # 11-20
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"ETH1_2N ETH2_2N ETH1_2P ETH2_2P NC NC ETH1_3P ETH2_3P ETH1_3N ETH2_3N " # 21-30
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"NC NC ETH1_4N ETH2_4N ETH1_4P ETH2_4P NC NC GND GND " # 31-40
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"R2 P5 P6 T6 R6 U7 T1 U6 T3 U5 " # 41-50
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"T4 V5 T4 U1 GND GND U2 H3 U3 J1 " # 51-60
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"V2 K1 V3 L1 W1 M1 Y1 J2 AA1 K2 " # 61-70
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"AB1 K3 W2 G3 Y2 J4 AB2 G4 AA3 F4 " # 71-80
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"AB3 L4 Y3 R3 W4 M3 AA4 V4 Y4 R4 " # 81-90
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"AB5 T5 AA5 J5 Y6 J6 AB6 W5 AA6 L5 " # 91-100
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"Y7 L6 AB7 W6 GND GND GND GND AA8 V7 " # 101-110
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"AB8 N13 Y8 N14 W7 P15 Y9 P16 V8 R16 " # 111-120
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"W9 N17 V9 V17 R14 P17 P14 U17 W17 T18 " # 121-130
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"Y18 R17 AA18 U18 W19 R18 AB18 N18 Y19 R19 " # 131-140
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"AA19 N19 V18 N15 V19 M16 AB20 M15 AA20 L15 " # 141-150
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"AA21 L16 AB21 K14 Y21 N22 GND GND AB22 J14 " # 151-160
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"W20 J15 Y22 J19 W21 H13 W22 H14 V20 H17 " # 161-170
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"V22 H15 U21 G18 U20 G17 T20 G16 P19 F16 " # 171-180
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"P20 F15 M18 E17 L19 E16 J17 D16 K18 D15 " # 181-190
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"K19 C18 K16 C17 H18 B20 H19 B17 NC NC" # 191-200
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)
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]
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def pmod_uart(port="P2"):
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if port == "P2":
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return [
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("serial", 0,
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Subsignal("tx", Pins("dimm:41")),
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Subsignal("rx", Pins("dimm:51")),
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IOStandard("LVCMOS33"))
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]
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else:
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raise ValueError(f"port {port} not in ['P2']")
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7a50tfgg484-1", _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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def create_programmer(self, cfg="openocd_xc7_ft2232.cfg"):
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return OpenOCD(cfg, "bscan_spi_xc7a50t.bit")
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
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@ -0,0 +1,186 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# Copyright (c) 2022 Victor Suarez Rovere <suarezvictor@gmail.com>
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# Copyright (c) 2023 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.gen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import colorlight_i9plus
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.dna import DNA
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from litedram.modules import M12L64322A
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from litedram.phy import GENSDRPHY
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq, with_dram=True, with_ethernet=True):
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self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_idelay = ClockDomain()
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if with_dram:
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self.cd_sys_ps = ClockDomain()
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# # #
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# Clk/Rst.
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clk25 = platform.request("clk25")
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# PLL.
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self.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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if with_dram:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) # untested
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# SDRAM clock
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sdram_clk = ClockSignal("sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="vivado", sys_clk_freq=100e6,
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with_dna = False,
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with_pmod_uart = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_port = 0,
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eth_ip = "192.168.1.50",
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eth_dynamic_ip = False,
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with_led_chaser = True,
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with_jtagbone = True,
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with_spi_flash = False,
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**kwargs):
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platform = colorlight_i9plus.Platform(toolchain=toolchain)
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# PMOD: uart on P2 (top) -------------------------------------------------------------------
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if with_pmod_uart:
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platform.add_extension(colorlight_i9plus.pmod_uart())
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# CRG --------------------------------------------------------------------------------------
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with_dram = (kwargs.get("integrated_main_ram_size", 0) == 0)
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self.crg = _CRG(platform, sys_clk_freq, with_dram)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", **kwargs)
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# DNA --------------------------------------------------------------------------------------
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if with_dna:
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self.dna = DNA()
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self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk)
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# SDRAM ------------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = GENSDRPHY
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self.sdrphy = sdrphy_cls(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = M12L64322A(sys_clk_freq, "1:1"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_port),
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pads = self.platform.request("eth", eth_port),
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tx_delay = 0)
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# Jtagbone ---------------------------------------------------------------------------------
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if with_jtagbone:
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self.add_jtagbone()
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import MX25L12833F
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=MX25L12833F(Codes.READ_1_1_4), rate="1:2", with_master=True)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq,
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)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.build.parser import LiteXArgumentParser
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parser = LiteXArgumentParser(platform=colorlight_i9plus.Platform, description="LiteX SoC on Arty A7.")
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parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
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parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
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parser.add_target_argument("--with-dna", action="store_true", help="Enable 7-Series DNA.")
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parser.add_target_argument("--with-pmod-uart", action="store_true", help="Enable uart on P2 (top) PMOD")
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ethopts = parser.target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_target_argument("--eth-port", default=0, type=int, help="Ethernet port to use (0/1)")
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parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
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parser.add_target_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = args.sys_clk_freq,
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with_dna = args.with_dna,
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with_pmod_uart = args.with_pmod_uart,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_port = args.eth_port,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_jtagbone = args.with_jtagbone,
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with_spi_flash = args.with_spi_flash,
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**parser.soc_argdict
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)
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builder = Builder(soc, **parser.builder_argdict)
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if args.build:
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builder.build(**parser.toolchain_argdict)
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if args.load:
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prog = soc.platform.create_programmer(cfg="prog/openocd_xc7_ft2232.cfg")
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer(cfg="prog/openocd_xc7_ft2232.cfg")
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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