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Merge pull request #58 from gsomlo/gls-trellisboard-spisdcard 

Move trellisboard target to SoCCore, add SPI-mode SDCard support
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enjoy-digital 2020-03-20 19:07:00 +01:00 committed by GitHub
parent fb1cab857a f021c1de5f
commit 33bf1d3ee2
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2 changed files with 42 additions and 48 deletions
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14
litex_boards/platforms/trellisboard.py
View File

@ -140,11 +140,19 @@ _io = [
Subsignal("uart_cts_n", Pins("P7"), IOStandard("LVCMOS33"))
),
("spisdcard", 0,
Subsignal("clk", Pins("AK3")),
Subsignal("mosi", Pins("AH3"), Misc("PULLMODE=UP")),
Subsignal("cs_n", Pins("AK1"), Misc("PULLMODE=UP")),
Subsignal("miso", Pins("AG1"), Misc("PULLMODE=UP")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
("sdcard", 0,
Subsignal("data", Pins("AG1 AJ1 AH1 AK1")),
Subsignal("clk", Pins("AK3")),
Subsignal("cmd", Pins("AH3")),
IOStandard("LVCMOS33")
Subsignal("cmd", Pins("AH3"), Misc("PULLMODE=UP")),
Subsignal("data", Pins("AG1 AJ1 AH1 AK1"), Misc("PULLMODE=UP")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
("spiflash4x", 0,

76
litex_boards/targets/trellisboard.py
View File

@ -13,6 +13,7 @@ from litex_boards.platforms import trellisboard
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
@ -20,7 +21,6 @@ from litedram.modules import MT41J256M16
from litedram.phy import ECP5DDRPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from liteeth.mac import LiteEthMAC
# CRG ----------------------------------------------------------------------------------------------
@ -78,8 +78,8 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs):
platform = trellisboard.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
@ -89,48 +89,29 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41J256M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, toolchain="trellis", **kwargs):
BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet ---------------------------------------------------------------------------------
# phy
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
# mac
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")
# timing constraints
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ethphy.crg.cd_eth_rx.clk,
self.ethphy.crg.cd_eth_tx.clk)
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Build --------------------------------------------------------------------------------------------
@ -145,10 +126,15 @@ def main():
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
parser.add_argument("--with-spi-sdcard", action="store_true",
help="enable SPI-mode SDCard support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
**soc_sdram_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs)