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targets: Move USB-ACM/ValentyUSB clone directly to LiteX to avoid duplication in targets.

This commit is contained in:
Florent Kermarrec 2022-04-21 15:43:50 +02:00
parent 4fbf2fc7de
commit 353aba0359
3 changed files with 7 additions and 17 deletions
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10
litex_boards/targets/gsd_orangecrab.py
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@ -149,16 +149,12 @@ class BaseSoC(SoCCore):
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name") in ["serial", "usb_acm"]
crg_cls = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll)
self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll=True)
# SoCCore ----------------------------------------------------------------------------------
if kwargs["uart_name"] in ["serial"]:
kwargs["uart_name"] = "usb_acm"
# Defaults to USB ACM through ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# Defaults to USB ACM through ValentyUSB.
kwargs["uart_name"] = "usb_acm"
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on OrangeCrab", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------

5
litex_boards/targets/kosagi_fomu.py
View File

@ -75,11 +75,8 @@ class BaseSoC(SoCCore):
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
# Enforce UART to USB-ACM
# Defaults to USB ACM through ValentyUSB.
kwargs["uart_name"] = "usb_acm"
# FIXME: do proper install of ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0

9
litex_boards/targets/logicbone.py
View File

@ -99,14 +99,11 @@ class BaseSoC(SoCCore):
platform = logicbone.Platform(revision=revision, device=device ,toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll=True)
# SoCCore ----------------------------------------------------------------------------------
if kwargs["uart_name"] == "usb_acm":
# FIXME: do proper install of ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# Defaults to USB ACM through ValentyUSB.
kwargs["uart_name"] = "usb_acm"
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Logicbone", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------