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efinix_trion_t120_bga576: Disable Identifier (crashes design) and move no_we, working.

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./efinix_trion_t120_bga576_dev_kit.py --build --load

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (b23a7321)

 Migen git sha1: 7507a2b
 LiteX git sha1: 8316fbf1

--=============== SoC ==================--
CPU:		VexRiscv @ 40MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
This commit is contained in:
Florent Kermarrec 2021-10-14 09:39:54 +02:00
parent 9145ff97d2
commit 36897f4646
1 changed files with 6 additions and 5 deletions
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11
litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
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@ -39,12 +39,13 @@ class BaseSoC(SoCCore):
platform = efinix_trion_t120_bga576_dev_kit.Platform() platform = efinix_trion_t120_bga576_dev_kit.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
kwargs["integrated_rom_no_we"] = True # FIXME: Avoid this.
kwargs["integrated_sram_no_we"] = True # FIXME: Avoid this.
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit", #ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit", # FIXME: Crash design.
ident_version = True, #ident_version = True,
**kwargs) integrated_rom_no_we = True, # FIXME: Avoid this.
integrated_sram_no_we = True, # FIXME: Avoid this.
**kwargs
)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform) self.submodules.crg = _CRG(platform)