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Merge pull request #134 from Disasm/fix-orangecrab 

Fix FPGA reset logic for orangecrab target
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enjoy-digital 2020-12-21 08:27:26 +01:00 committed by GitHub
parent e1f9fd1a25 f6a106cdf4
commit 36b7fb1033
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litex_boards/targets/orangecrab.py
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@ -69,7 +69,7 @@ class _CRG(Module):
reset_timer = WaitTimer(sys_clk_freq) reset_timer = WaitTimer(sys_clk_freq)
self.submodules += reset_timer self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n) self.comb += reset_timer.wait.eq(~rst_n)
self.comb += platform.request("rst_n").eq(reset_timer.done) self.comb += platform.request("rst_n").eq(~reset_timer.done)
class _CRGSDRAM(Module): class _CRGSDRAM(Module):