Merge pull request #134 from Disasm/fix-orangecrab

Fix FPGA reset logic for orangecrab target
2020-12-21 08:27:26 +01:00 · 2020-12-21 08:27:26 +01:00 · 36b7fb1033
parent e1f9fd1a25 f6a106cdf4
commit 36b7fb1033
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/targets/orangecrab.py
+++ b/litex_boards/targets/orangecrab.py
@ -69,7 +69,7 @@ class _CRG(Module):
        reset_timer = WaitTimer(sys_clk_freq)
        self.submodules += reset_timer
        self.comb += reset_timer.wait.eq(~rst_n)
-        self.comb += platform.request("rst_n").eq(reset_timer.done)
+        self.comb += platform.request("rst_n").eq(~reset_timer.done)


 class _CRGSDRAM(Module):