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litex_acorn_baseboard: Add SPIFlash support.

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This commit is contained in:
Florent Kermarrec 2021-10-15 18:21:21 +02:00
parent bdf2848208
commit 3730d96709
2 changed files with 18 additions and 1 deletions

8
litex_boards/platforms/litex_acorn_baseboard.py
View file

@ -34,6 +34,14 @@ _io = [
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash4x", 0,
Subsignal("cs_n", Pins("R2")),
#Subsignal("clk", Pins("U3")),
Subsignal("dq", Pins("W2 V2 Y2 W1")),
IOStandard("LVCMOS33")
),
# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("M1")),

11
litex_boards/targets/litex_acorn_baseboard.py
View file

@ -64,6 +64,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6),
with_spi_flash = False,
with_ethernet = False,
with_etherbone = False,
with_video_terminal = False,
@ -80,6 +81,12 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
@ -119,7 +126,8 @@ def main():
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
parser.add_argument("--with-lcd", action="store_true", help="Enable OLED LCD support")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
parser.add_argument("--with-lcd", action="store_true", help="Enable OLED LCD support")
builder_args(parser)
soc_core_args(parser)
@ -128,6 +136,7 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_spi_flash = args.with_spi_flash,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
with_video_terminal = args.with_video_terminal,