Addition of USB ACM for ECP5
This commit is contained in:
Dave Marples
parent
a12faae0fb
commit
389e8aa13a
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@ -172,6 +172,13 @@ _io_v7_0 = [ # Documented by @miek
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Subsignal("tx_data", Pins("T14 R12 R13 R14")),
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IOStandard("LVCMOS33")
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),
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("usb", 0,
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Subsignal("d_p", Pins("M8")),
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Subsignal("d_n", Pins("R2")),
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Subsignal("pullup", Pins("P4")),
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IOStandard("LVCMOS33")
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),
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]
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# from https://github.com/miek/chubby75/blob/5a-75b-v7_pinout/5a-75b/hardware_V6.1.md
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@ -84,6 +84,13 @@ _io = [
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Subsignal("n", Pins("C10")),
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IOStandard("LVCMOS33")
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),
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("usb", 0,
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Subsignal("d_p", Pins("D15")),
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Subsignal("d_n", Pins("E15")),
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Subsignal("pullup", Pins("B12 C12")),
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IOStandard("LVCMOS33")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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@ -0,0 +1,26 @@
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USB
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===
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USB support has been integrated for the V7.0 this board. Supporting other
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versions should be trivial and just need pinning changes. To build with
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usb support just do;
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./colourlight_5a_75b.py --uart-name=usb_cdc
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To install onto the board;
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./colourlight_5a_75b.py --load
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The USB Serial connection will appear as /dev/ttyACMx, or equivalent on your OS.
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Pinning for V7.0;
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* Replace U23 with a SN74CBT3245APWR, or remove U23 and place jumper wires.
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(You're basically making the ports Bi-directional).
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* Place a 15K resistor between J4 pin 2 and J4 pin 4.
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* Place a 15K resistor between J4 pin 3 and J4 pin 4.
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* Place a 1.5K resistor between J4 pin 1 and J4 pin 3.
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* Connect USB DP (Green) to J4 pin 3, USB DN (White) to J4 pin 2.
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@ -0,0 +1,11 @@
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USB
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===
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USB support has been integrated and tested for V3.0.3 this board. Revisions
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higher than this should be supported. The USB connection is on US2.
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To build with usb support just do;
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./ulx3s.py --uart-name=usb_cdc
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The USB Serial connection will appear as /dev/ttyACMx, or equivalent on your OS.
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@ -48,7 +48,7 @@ from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_rst=True):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False, with_rst=True):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain()
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@ -67,22 +67,34 @@ class _CRG(Module):
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
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# USB PLL
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if with_usb_pll:
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self.submodules.usb_pll = usb_pll = ECP5PLL()
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usb_pll.register_clkin(clk25, 25e6)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
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#self.comb += self.cd_usb_48.clk.eq(self.cd_sys.clk)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, revision, with_ethernet=False, with_etherbone=False, **kwargs):
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def __init__(self, revision, with_ethernet=False, with_etherbone=False, sys_clk_freq=60e6, **kwargs):
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platform = colorlight_5a_75b.Platform(revision=revision)
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sys_clk_freq = int(125e6) if with_etherbone else int(60e6)
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if (with_etherbone):
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sys_clk_freq = int(125e6)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_rst=with_rst)
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with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll=with_usb_pll,with_rst=with_rst)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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@ -115,21 +127,33 @@ class BaseSoC(SoCCore):
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# Load ---------------------------------------------------------------------------------------------
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def load():
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def load(iface="ftdi"):
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import os
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f = open("openocd.cfg", "w")
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f.write(
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"""
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interface ftdi
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if (iface == "ftdi"):
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f.write(
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"""adapter driver ftdi
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ftdi_vid_pid 0x0403 0x6011
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ftdi_channel 0
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ftdi_layout_init 0x0098 0x008b
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reset_config none
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adapter_khz 25000
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adapter speed 25000
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jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
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""")
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elif (iface=="jlink"):
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f.write("""adapter driver jlink
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transport select jtag
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reset_config none
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telnet_port 4444
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adapter speed 10000
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jtag newtap lfe5u25 tap -irlen 8 -irmask 0xFF -ircapture 0x5 -expected-id 0x41111043
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""")
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else:
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print("Unrecognised jtag interface")
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exit()
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f.close()
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os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_basesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
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os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf -tap lfe5u25.tap -quiet -progress soc_basesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
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exit()
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# Build --------------------------------------------------------------------------------------------
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@ -144,15 +168,20 @@ def main():
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parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
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parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
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parser.add_argument("--load", action="store_true", help="load bitstream")
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parser.add_argument("--iface", default="ftdi", help="loading jtag interface")
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parser.add_argument("--sys-clk-freq", default=60e6,
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help="system clock frequency (default=60MHz)")
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args = parser.parse_args()
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if args.load:
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load()
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load(iface=args.iface)
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assert not (args.with_ethernet and args.with_etherbone)
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soc = BaseSoC(revision=args.revision,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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sys_clk_freq = args.sys_clk_freq,
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**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**trellis_argdict(args))
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@ -27,7 +27,7 @@ from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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@ -42,10 +42,17 @@ class _CRG(Module):
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq, margin=0)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
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# USB PLL
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if with_usb_pll:
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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self.comb += self.cd_usb_48.clk.eq(self.cd_sys.clk)
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# SDRAM clock
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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@ -64,7 +71,8 @@ class BaseSoC(SoCCore):
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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@ -87,8 +95,8 @@ def main():
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help="gateware toolchain to use, trellis (default) or diamond")
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parser.add_argument("--device", dest="device", default="LFE5U-45F",
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help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
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parser.add_argument("--sys-clk-freq", default=50e6,
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help="system clock frequency (default=50MHz)")
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parser.add_argument("--sys-clk-freq", default=48e6,
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help="system clock frequency (default=48MHz)")
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parser.add_argument("--sdram-module", default="MT48LC16M16",
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help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
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builder_args(parser)
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