Fixup.

litex_boards/platforms/digilent_cmod_a7.py

@@ -65,10 +65,11 @@ class Platform(XilinxPlatform):
 
     def __init__(self, variant="a7-35", toolchain="vivado"):
         device = {
-                "a7-35": "xc7a35t-cpg236-1"
+                "a7-35": "xc7a35tcpg236-1"
                 }[variant]
         XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
 
     def do_finalize(self,fragment):
         XilinxPlatform.do_finalize(self, fragment)
+        from litex.build.xilinx import symbiflow
         self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)