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targets/add_constant: avoid specifying value when value is None (=default)

This commit is contained in:
Florent Kermarrec 2020-03-26 09:46:29 +01:00
parent 555bf6c4dc
commit 3b91e96c42
8 changed files with 12 additions and 12 deletions
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2
litex_boards/targets/camlink_4k.py
View File

@ -85,7 +85,7 @@ class BaseSoC(SoCCore):
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.add_constant("ECP5DDRPHY")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,

4
litex_boards/targets/kcu105.py
View File

@ -67,8 +67,8 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 200e6,
cmd_latency = 0)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
self.add_constant("USDDRPHY_DEBUG", None)
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram",
phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"),

4
litex_boards/targets/mercury_xu5.py
View File

@ -66,8 +66,8 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6,
cmd_latency = 0)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
self.add_constant("USDDRPHY_DEBUG", None)
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT40A256M16(sys_clk_freq, "1:4"),

2
litex_boards/targets/orangecrab.py
View File

@ -116,7 +116,7 @@ class BaseSoC(SoCCore):
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.add_constant("ECP5DDRPHY")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,

2
litex_boards/targets/trellisboard.py
View File

@ -94,7 +94,7 @@ class BaseSoC(SoCCore):
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.add_constant("ECP5DDRPHY")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"),

4
litex_boards/targets/vcu118.py
View File

@ -66,8 +66,8 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6,
cmd_latency = 0)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
self.add_constant("USDDRPHY_DEBUG", None)
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram",
phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"),

2
litex_boards/targets/versa_ecp5.py
View File

@ -87,7 +87,7 @@ class BaseSoC(SoCCore):
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.add_constant("ECP5DDRPHY")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,

4
litex_boards/targets/zcu104.py
View File

@ -65,8 +65,8 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6,
cmd_latency = 1)
self.add_csr("ddrphy")
self.add_constant("USDDRPHY", None)
self.add_constant("USDDRPHY_DEBUG", None)
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram",
phy = self.ddrphy,
module = KVR21SE15S84(sys_clk_freq, "1:4"),