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Merge pull request #313 from fjullien/add_io_to_t120 

efinix: add clock pins to t120 bga576 platform
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enjoy-digital 2022-01-03 16:07:54 +01:00 committed by GitHub
parent b5008a2d5c 379745b039
commit 3dd85d9afb
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1 changed files with 6 additions and 0 deletions
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litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py
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@ -14,6 +14,9 @@ from litex.build.efinix import EfinixProgrammer
_io = [ _io = [
# Clk # Clk
("clk40", 0, Pins("P19"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), ("clk40", 0, Pins("P19"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
("clk50", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
("clk20", 0, Pins("AA9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
("clk74_25", 0, Pins("J9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
# Leds # Leds
("user_led", 0, Pins("AB16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")), ("user_led", 0, Pins("AB16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
@ -92,6 +95,9 @@ _io = [
# DRAM. # DRAM.
("dram_pll_refclk", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), ("dram_pll_refclk", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
# MIPI
("mipi_refclk", 0, Pins("G9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")),
] ]
# Bank voltage --------------------------------------------------------------------------------------- # Bank voltage ---------------------------------------------------------------------------------------