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targets/fpc_iii: review/cleanup to increase similarities with others targets to ease maintenance.

This commit is contained in:
Florent Kermarrec 2021-01-29 08:46:31 +01:00
parent 6c6d8a1393
commit 3deeb69531
1 changed files with 14 additions and 19 deletions
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33
litex_boards/targets/fpc_iii.py
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@ -37,7 +37,7 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.stop = Signal() self.stop = Signal()
self.reset = Signal() self.reset = Signal()
@ -84,7 +84,9 @@ class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, **kwargs): def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, **kwargs):
platform = fpc_iii.Platform(toolchain=toolchain) platform = fpc_iii.Platform(toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs[ "uart_name" ] == "serial": if kwargs[ "uart_name" ] == "serial":
# Defaults to USB FIFO since no real serial.
kwargs[ "uart_name" ] = "usb_fifo" kwargs[ "uart_name" ] = "usb_fifo"
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
@ -99,17 +101,11 @@ class BaseSoC(SoCCore):
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:
ddram = platform.request("ddram") ddram = platform.request("ddram")
# Pin K16 (PR29A) is available as the true component of a self.submodules.ddrphy = ECP5DDRPHY(ddram, sys_clk_freq, clk_polarity=1) # clk_p/n swapped.
# differential pair, and K17 (PR29B) is its complement.
# So the clk_polarity=1 parameter would be necessary only if
# some idiot were laying out the board and wired K16 to
# the DDR3 CK-, and K17 to CK+. The chances of that
# happening are remote, of course.
self.submodules.ddrphy = ECP5DDRPHY( ddram, sys_clk_freq, clk_polarity=1 )
self.ddrphy.settings.rtt_nom = "disabled" self.ddrphy.settings.rtt_nom = "disabled"
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.comb += ddram.vccio.eq( Replicate( C(1), ddram.vccio.nbits ) ) self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
@ -120,8 +116,7 @@ class BaseSoC(SoCCore):
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True l2_cache_reverse = True
) )
self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1)
self.comb += platform.request("dram_vtt_en").eq( 0 if self.integrated_main_ram_size else 1 )
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone: if with_ethernet or with_etherbone:
@ -144,14 +139,14 @@ class BaseSoC(SoCCore):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on FPC-III") parser = argparse.ArgumentParser(description="LiteX SoC on FPC-III")
parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=80e6, help="system clock frequency (default=80MHz)") parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency (default=80MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="enable Ethernet wishbone support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Ethernet wishbone support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
trellis_args(parser) trellis_args(parser)