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platforms/targets: Fix typos.

This commit is contained in:
Florent Kermarrec 2022-02-14 17:26:46 +01:00
parent b53b79821e
commit 3f58df9974
3 changed files with 13 additions and 5 deletions
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2
litex_boards/platforms/digilent_zedboard.py
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@ -205,7 +205,7 @@ class Platform(XilinxPlatform):
default_clk_period = 1e9/100e6 default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"): def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain=toolchains) XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \ self.toolchain.bitstream_commands = \
["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ] ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]

8
litex_boards/targets/digilent_arty_z7.py
View File

@ -39,10 +39,14 @@ class _CRG(Module):
self.comb += ClockSignal("sys").eq(ClockSignal("ps7")) self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst) self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
else: else:
# Clk.
clk125 = platform.request("clk125")
# PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-1) self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst) self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq) pll.register_clkin(clk125, 125e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
# Ignore sys_clk to pll.clkin path created by SoC's rst. # Ignore sys_clk to pll.clkin path created by SoC's rst.
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)

8
litex_boards/targets/digilent_zedboard.py
View File

@ -37,10 +37,14 @@ class _CRG(Module):
self.comb += ClockSignal("sys").eq(ClockSignal("ps7")) self.comb += ClockSignal("sys").eq(ClockSignal("ps7"))
self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst) self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst)
else: else:
# Clk.
clk100 = platform.request("clk100")
# PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-1) self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst) self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq) pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
# Ignore sys_clk to pll.clkin path created by SoC's rst. # Ignore sys_clk to pll.clkin path created by SoC's rst.
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)