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targets/orangecrab: add USB PLL for USB CDC with ValentyUSB.

This commit is contained in:
Florent Kermarrec 2020-03-25 19:38:36 +01:00
parent 85f38876c2
commit 4053c02d7e
1 changed files with 14 additions and 4 deletions
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16
litex_boards/targets/orangecrab.py
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@ -23,7 +23,7 @@ from litedram.phy import ECP5DDRPHY
# _CRG ---------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
@ -72,6 +72,16 @@ class _CRG(Module):
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
]
# USB PLL
if with_usb_pll:
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll = ECP5PLL()
self.submodules += usb_pll
usb_pll.register_clkin(clk48, 48e6)
usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
@ -88,8 +98,8 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
with_usb_pll = kwargs.get("uart_name", None) == "usb_cdc"
self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: