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targets: manual define of the SDRAM PHY is no longer needed.

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This commit is contained in:
Florent Kermarrec 2020-04-16 11:25:59 +02:00
parent cb95962850
commit 4185a019f5
8 changed files with 0 additions and 8 deletions

1
litex_boards/targets/camlink_4k.py
View file

@ -85,7 +85,6 @@ class BaseSoC(SoCCore):
platform.request("ddram"), platform.request("ddram"),
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

1
litex_boards/targets/kcu105.py
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@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 200e6, iodelay_clk_freq = 200e6,
cmd_latency = 0) cmd_latency = 0)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG") self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

1
litex_boards/targets/mercury_xu5.py
View file

@ -66,7 +66,6 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
cmd_latency = 0) cmd_latency = 0)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG") self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

1
litex_boards/targets/orangecrab.py
View file

@ -116,7 +116,6 @@ class BaseSoC(SoCCore):
platform.request("ddram"), platform.request("ddram"),
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

1
litex_boards/targets/trellisboard.py
View file

@ -94,7 +94,6 @@ class BaseSoC(SoCCore):
platform.request("ddram"), platform.request("ddram"),
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"), module = MT41J256M16(sys_clk_freq, "1:2"),

1
litex_boards/targets/vcu118.py
View file

@ -66,7 +66,6 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
cmd_latency = 0) cmd_latency = 0)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG") self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

1
litex_boards/targets/versa_ecp5.py
View file

@ -87,7 +87,6 @@ class BaseSoC(SoCCore):
platform.request("ddram"), platform.request("ddram"),
sys_clk_freq=sys_clk_freq) sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,

1
litex_boards/targets/zcu104.py
View file

@ -65,7 +65,6 @@ class BaseSoC(SoCCore):
iodelay_clk_freq = 500e6, iodelay_clk_freq = 500e6,
cmd_latency = 1) cmd_latency = 1)
self.add_csr("ddrphy") self.add_csr("ddrphy")
self.add_constant("USDDRPHY")
self.add_constant("USDDRPHY_DEBUG") self.add_constant("USDDRPHY_DEBUG")
self.add_sdram("sdram", self.add_sdram("sdram",
phy = self.ddrphy, phy = self.ddrphy,