Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

targets: cleanup Altera CRGs

Browse source
This commit is contained in:
Florent Kermarrec 2020-01-09 19:46:39 +01:00
parent 9e9fc5ef78
commit 4192b20f09
4 changed files with 84 additions and 53 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
litex_boards/community/targets/de10lite.py
View file

@ -29,10 +29,11 @@ class _CRG(Module):
# # #
# main input clock for PLL
# Clk / Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9/50e6)
# sys clk / sdram clk / vga_clk from PLL
# PLL
pll_locked = Signal()
pll_clk_out = Signal(6)
self.specials += \
@ -52,8 +53,6 @@ class _CRG(Module):
p_CLK2_PHASE_SHIFT = "0",
p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000,
p_INTENDED_DEVICE_FAMILY = "MAX 10",
p_LPM_TYPE = "altpll",
p_OPERATION_MODE = "NORMAL",
i_INCLK = clk50,
o_CLK = pll_clk_out,
@ -72,8 +71,10 @@ class _CRG(Module):
self.specials += [
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked),
AsyncResetSynchronizer(self.cd_vga, ~pll_locked),
AsyncResetSynchronizer(self.cd_vga, ~pll_locked)
]
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------

42
litex_boards/community/targets/de1soc.py
View file

@ -6,6 +6,7 @@
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import de1soc
@ -21,41 +22,50 @@ class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# sys clk / sdram clk
# Clk / Rst
clk50 = platform.request("clk50")
self.comb += self.cd_sys.clk.eq(clk50)
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
pll_locked = Signal()
pll_clk_out = Signal(6)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE = "AUTO",
p_CLK0_DIVIDE_BY = 1,
p_CLK0_DUTY_CYCLE = 50,
p_CLK0_MULTIPLY_BY = 1,
p_CLK0_PHASE_SHIFT = "-3000",
p_CLK0_PHASE_SHIFT = "0",
p_CLK1_DIVIDE_BY = 1,
p_CLK1_DUTY_CYCLE = 50,
p_CLK1_MULTIPLY_BY = 1,
p_CLK1_PHASE_SHIFT = "-10000",
p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000,
p_OPERATION_MODE = "ZERO_DELAY_BUFFER",
p_OPERATION_MODE = "NORMAL",
i_INCLK = clk50,
o_CLK = self.cd_sys_ps.clk,
i_ARESET = ~rst_n,
o_CLK = pll_clk_out,
i_ARESET = 0,
i_CLKENA = 0x3f,
i_EXTCLKENA = 0xf,
i_FBIN = 1,
i_PFDENA = 1,
i_PLLENA = 1,
o_LOCKED = pll_locked,
)
self.comb += [
self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]),
]
self.specials += [
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
]
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------

42
litex_boards/community/targets/de2_115.py
View file

@ -6,6 +6,7 @@
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import de2_115
@ -21,41 +22,50 @@ class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
# power on rst
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# sys clk / sdram clk
# Clk / Rst
clk50 = platform.request("clk50")
self.comb += self.cd_sys.clk.eq(clk50)
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
pll_locked = Signal()
pll_clk_out = Signal(6)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE = "AUTO",
p_CLK0_DIVIDE_BY = 1,
p_CLK0_DUTY_CYCLE = 50,
p_CLK0_MULTIPLY_BY = 1,
p_CLK0_PHASE_SHIFT = "-3000",
p_CLK0_PHASE_SHIFT = "0",
p_CLK1_DIVIDE_BY = 1,
p_CLK1_DUTY_CYCLE = 50,
p_CLK1_MULTIPLY_BY = 1,
p_CLK1_PHASE_SHIFT = "-10000",
p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000,
p_OPERATION_MODE = "ZERO_DELAY_BUFFER",
p_OPERATION_MODE = "NORMAL",
i_INCLK = clk50,
o_CLK = self.cd_sys_ps.clk,
i_ARESET = ~rst_n,
o_CLK = pll_clk_out,
i_ARESET = 0,
i_CLKENA = 0x3f,
i_EXTCLKENA = 0xf,
i_FBIN = 1,
i_PFDENA = 1,
i_PLLENA = 1,
o_LOCKED = pll_locked,
)
self.comb += [
self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]),
]
self.specials += [
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
]
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------

42
litex_boards/official/targets/de0nano.py
View file

@ -6,6 +6,7 @@
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import de0nano
@ -21,41 +22,50 @@ class _CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
# Power on reset
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(~rst_n),
self.cd_sys_ps.rst.eq(~rst_n)
]
# Sys Clk / SDRAM Clk
# Clk / Rst
clk50 = platform.request("clk50")
self.comb += self.cd_sys.clk.eq(clk50)
platform.add_period_constraint(clk50, 1e9/50e6)
# PLL
pll_locked = Signal()
pll_clk_out = Signal(6)
self.specials += \
Instance("ALTPLL",
p_BANDWIDTH_TYPE = "AUTO",
p_CLK0_DIVIDE_BY = 1,
p_CLK0_DUTY_CYCLE = 50,
p_CLK0_MULTIPLY_BY = 1,
p_CLK0_PHASE_SHIFT = "-3000",
p_CLK0_PHASE_SHIFT = "0",
p_CLK1_DIVIDE_BY = 1,
p_CLK1_DUTY_CYCLE = 50,
p_CLK1_MULTIPLY_BY = 1,
p_CLK1_PHASE_SHIFT = "-10000",
p_COMPENSATE_CLOCK = "CLK0",
p_INCLK0_INPUT_FREQUENCY = 20000,
p_OPERATION_MODE = "ZERO_DELAY_BUFFER",
p_OPERATION_MODE = "NORMAL",
i_INCLK = clk50,
o_CLK = self.cd_sys_ps.clk,
i_ARESET = ~rst_n,
o_CLK = pll_clk_out,
i_ARESET = 0,
i_CLKENA = 0x3f,
i_EXTCLKENA = 0xf,
i_FBIN = 1,
i_PFDENA = 1,
i_PLLENA = 1,
o_LOCKED = pll_locked,
)
self.comb += [
self.cd_sys.clk.eq(pll_clk_out[0]),
self.cd_sys_ps.clk.eq(pll_clk_out[1]),
]
self.specials += [
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked)
]
# SDRAM clock
self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
# BaseSoC ------------------------------------------------------------------------------------------