Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

platforms: always use 1e9/clk_freq for default_clk_period

This commit is contained in:
Florent Kermarrec 2020-01-09 19:28:50 +01:00
parent fe23881348
commit 9e9fc5ef78
5 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex_boards/partner/platforms/aller.py
View File

@ -105,7 +105,7 @@ _io = [
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")

2
litex_boards/partner/platforms/nereid.py
View File

@ -380,7 +380,7 @@ _connectors = [
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k160t-fbg676-1", _io, _connectors,

2
litex_boards/partner/platforms/orangecrab.py
View File

@ -56,7 +56,7 @@ _io = [
class Platform(LatticePlatform):
default_clk_name = "clk48"
default_clk_period = int(1e9/48e6)
default_clk_period = 1e9/48e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, **kwargs)

2
litex_boards/partner/platforms/tagus.py
View File

@ -153,7 +153,7 @@ _connectors = [
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain="vivado")

2
litex_boards/partner/platforms/trellisboard.py
View File

@ -204,7 +204,7 @@ _connectors = [
class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 83
default_clk_period = 1e9/12e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG756C", _io, _connectors, **kwargs)