zedboard: compress bitstream, derive default clk f

2021-12-22 03:13:30 +01:00 · 2021-12-22 03:13:30 +01:00 · 43a1e13b53
parent 166451e65e
commit 43a1e13b53
1 changed files with 3 additions and 0 deletions
--- a/litex_boards/platforms/digilent_zedboard.py
+++ b/litex_boards/platforms/digilent_zedboard.py
@ -206,6 +206,9 @@ class Platform(XilinxPlatform):

    def __init__(self):
        XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain="vivado")
+        self.toolchain.bitstream_commands = \
+            ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]
+        self.default_clk_freq = 1e9 / self.default_clk_period

    def create_programmer(self):
        return OpenOCD(config="board/digilent_zedboard.cfg")