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zedboard: compress bitstream, derive default clk f

This commit is contained in:
Ilia Sergachev 2021-12-22 03:13:30 +01:00
parent 166451e65e
commit 43a1e13b53
1 changed files with 3 additions and 0 deletions
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3
litex_boards/platforms/digilent_zedboard.py
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@ -206,6 +206,9 @@ class Platform(XilinxPlatform):
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ]
self.default_clk_freq = 1e9 / self.default_clk_period
def create_programmer(self): def create_programmer(self):
return OpenOCD(config="board/digilent_zedboard.cfg") return OpenOCD(config="board/digilent_zedboard.cfg")