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targets: remove add_csr("crg") (no longer needed).

This commit is contained in:
Florent Kermarrec 2020-11-12 11:54:11 +01:00
parent bd4e92ad13
commit 4401fec1e6
4 changed files with 0 additions and 4 deletions
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1
litex_boards/targets/acorn_cle_215.py
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@ -87,7 +87,6 @@ class BaseSoC(SoCCore):
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq) self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:

1
litex_boards/targets/aller.py
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@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq) self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:

1
litex_boards/targets/nereid.py
View File

@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq) self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size:

1
litex_boards/targets/tagus.py
View File

@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq) self.submodules.crg = CRG(platform, sys_clk_freq)
self.add_csr("crg")
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size: if not self.integrated_main_ram_size: