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colorlight_5a_75b: minor comment changes.

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This commit is contained in:
Florent Kermarrec 2020-04-09 08:14:17 +02:00
parent 7157b40718
commit 467b14a0ad
2 changed files with 4 additions and 4 deletions
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3
litex_boards/platforms/colorlight_5a_75b.py
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@ -20,11 +20,10 @@ _io_v6_1 = [ # Documented by @smunaut
("user_btn_n", 0, Pins("R16"), IOStandard("LVCMOS33")),
# serial
# There seems to be some capacitance on KEY+ pin, so high baudrates may not work (>9600bps).
("serial", 0,
Subsignal("tx", Pins("U16")), # led (J19 DATA_LED-)
Subsignal("rx", Pins("R16")), # btn (J19 KEY+)
# It seems there's some capacitance on the KEY+ pin, so bigger baudrates
# may not work
IOStandard("LVCMOS33")
),

5
litex_boards/targets/colorlight_5a_75b.py
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@ -7,12 +7,13 @@
#
# 1) SoC with regular UART and optional Ethernet connected to the CPU:
# Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+.
# ./colorlight_5a_75b.py --uart-baudrate 9600 (add --with-ethernet to add Ethernet capability)
# ./colorlight_5a_75b.py --revision=7.0 (or 6.1) (--with-ethernet to add Ethernet capability)
# Note: on revision 6.1, add --uart-baudrate=9600 to lower the baudrate.
# ./colorlight_5a_75b.py --load
# You should see the LiteX BIOS and be able to interact with it.
#
# 2) SoC with UART in crossover mode over Etherbone:
# ./colorlight_5a_75b.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv
# ./colorlight_5a_75b.py --revision=7.0 (or 6.1) --uart-name=crossover --with-etherbone --csr-csv=csr.csv
# ./colorlight_5a_75b.py --load
# ping 192.168.1.50
# Get and install wishbone tool from: https://github.com/litex-hub/wishbone-utils/releases