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targets: Use new CSR automatic allocation (self.add_csr will still work but is no longer required).

This commit is contained in:
Florent Kermarrec 2021-03-25 10:11:24 +01:00
parent b3786c5e52
commit 47bdf5f759
59 changed files with 1 additions and 140 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex_boards/targets/ac701.py
View File

@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
@ -94,7 +93,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
# 1000BaseX Ethernet PHY ---------------------------------------------------------------
if eth_phy == "1000basex":
@ -129,14 +127,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------
def main():

4
litex_boards/targets/acorn_cle_215.py
View File

@ -91,7 +91,6 @@ class BaseSoC(SoCCore):
nphases = 4,
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K512M16(sys_clk_freq, "1:4"),
@ -107,7 +106,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
@ -140,7 +138,6 @@ class BaseSoC(SoCCore):
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
@ -149,7 +146,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/aller.py
View File

@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
nphases = 4,
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
@ -91,14 +90,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/alveo_u250.py
View File

@ -77,7 +77,6 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
is_rdimm = True)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
@ -96,14 +95,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

4
litex_boards/targets/alveo_u280.py
View File

@ -64,7 +64,6 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Alveo U280",
ident_version = True,
# bus_standard = "axi-lite", #
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -77,7 +76,6 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6,
is_rdimm = True)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MTA18ASF2G72PZ(sys_clk_freq, "1:4"),
@ -96,14 +94,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("gpio_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/arrow_sockit.py
View File

@ -130,7 +130,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
if mister_sdram == "xs_v22":
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY

3
litex_boards/targets/arty.py
View File

@ -73,7 +73,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
@ -89,7 +88,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
@ -103,7 +101,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/arty_s7.py
View File

@ -69,7 +69,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
@ -84,7 +83,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/c10lprefkit.py
View File

@ -93,14 +93,12 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/camlink_4k.py
View File

@ -90,7 +90,6 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,
@ -107,7 +106,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/colorlight_5a_75x.py
View File

@ -167,7 +167,6 @@ class BaseSoC(SoCCore):
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -178,7 +177,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/colorlight_i5.py
View File

@ -122,7 +122,6 @@ class BaseSoC(SoCCore):
# Leds -------------------------------------------------------------------------------------
ledn = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
@ -151,7 +150,6 @@ class BaseSoC(SoCCore):
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -174,7 +172,6 @@ class BaseSoC(SoCCore):
# PRBS -------------------------------------------------------------------------------------
if with_prbs:
self.submodules.prbs = _PRBSSource()
self.add_csr("prbs")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/crosslink_nx_evn.py
View File

@ -96,8 +96,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(14)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/crosslink_nx_vip.py
View File

@ -101,8 +101,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/de0nano.py
View File

@ -89,7 +89,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/de10lite.py
View File

@ -88,7 +88,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/de10nano.py
View File

@ -99,7 +99,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/deca.py
View File

@ -71,7 +71,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/ecp5_evn.py
View File

@ -62,7 +62,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/ecpix5.py
View File

@ -95,7 +95,6 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
@ -114,7 +113,6 @@ class BaseSoC(SoCCore):
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
rx_delay = 0e-9)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -129,7 +127,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = Cat(leds_pads),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

4
litex_boards/targets/fk33.py
View File

@ -63,7 +63,6 @@ class BaseSoC(SoCCore):
data_width = 128,
bar0_size = 0x20000)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk)
self.add_csr("pcie_phy")
# Endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, max_pending_requests=8)
@ -77,13 +76,11 @@ class BaseSoC(SoCCore):
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = True, buffering_depth=1024,
with_loopback = True)
self.add_csr("pcie_dma0")
self.add_constant("DMA_CHANNELS", 1)
# MSI
self.submodules.pcie_msi = LitePCIeMSI()
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
@ -97,7 +94,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/fomu.py
View File

@ -113,7 +113,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Flash --------------------------------------------------------------------------------------------

3
litex_boards/targets/fpc_iii.py
View File

@ -105,7 +105,6 @@ class BaseSoC(SoCCore):
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = IS43TR16256A(sys_clk_freq, "1:2"),
@ -122,7 +121,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -132,7 +130,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/genesys2.py
View File

@ -65,7 +65,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:4"),
@ -81,7 +80,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -91,7 +89,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/icebreaker.py
View File

@ -114,7 +114,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Flash --------------------------------------------------------------------------------------------

5
litex_boards/targets/kc705.py
View File

@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
@ -87,7 +86,6 @@ class BaseSoC(SoCCore):
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
clk_freq = self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
@ -95,7 +93,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
@ -128,7 +125,6 @@ class BaseSoC(SoCCore):
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
@ -137,7 +133,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

5
litex_boards/targets/kcu105.py
View File

@ -79,7 +79,6 @@ class BaseSoC(SoCCore):
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"),
@ -95,7 +94,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_eth.clk,
data_pads = self.platform.request("sfp", 0),
sys_clk_freq = self.clk_freq)
self.add_csr("ethphy")
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
if with_ethernet:
@ -108,7 +106,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
@ -141,7 +138,6 @@ class BaseSoC(SoCCore):
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
@ -150,7 +146,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/kx2.py
View File

@ -64,7 +64,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = H5TC4G63CFR(sys_clk_freq, "1:4"),
@ -79,7 +78,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/linsn_rv901t.py
View File

@ -80,14 +80,12 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/litefury.py
View File

@ -75,7 +75,6 @@ class BaseSoC(SoCCore):
nphases = 4,
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = AS4C256M16D3A(sys_clk_freq, "1:4"),
@ -91,14 +90,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 64,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/logicbone.py
View File

@ -125,7 +125,6 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
@ -143,7 +142,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
@ -151,7 +149,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/mercury_xu5.py
View File

@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT40A256M16(sys_clk_freq, "1:4"),
@ -87,7 +86,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/mimas_a7.py
View File

@ -69,7 +69,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
@ -85,14 +84,12 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/minispartan6.py
View File

@ -106,7 +106,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/mist.py
View File

@ -88,7 +88,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/nereid.py
View File

@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
nphases = 4,
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8KTF51264(sys_clk_freq, "1:4", speedgrade="800"),
@ -88,7 +87,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Build --------------------------------------------------------------------------------------------

4
litex_boards/targets/netv2.py
View File

@ -79,7 +79,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = K4B2G1646F(sys_clk_freq, "1:4"),
@ -95,7 +94,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
@ -103,14 +101,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1, max_pending_requests=2)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/nexys4ddr.py
View File

@ -72,7 +72,6 @@ class BaseSoC(SoCCore):
memtype = "DDR2",
nphases = 2,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT47H64M16(sys_clk_freq, "1:2"),
@ -88,7 +87,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -106,7 +104,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

4
litex_boards/targets/nexys_video.py
View File

@ -78,7 +78,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K256M16(sys_clk_freq, "1:4"),
@ -94,7 +93,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# SATA -------------------------------------------------------------------------------------
@ -122,7 +120,6 @@ class BaseSoC(SoCCore):
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
@ -139,7 +136,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/orangecrab.py
View File

@ -184,7 +184,6 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq,
cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
self.ddrphy.settings.rtt_nom = "disabled"
self.add_csr("ddrphy")
if hasattr(ddram_pads, "vccio"):
self.comb += ddram_pads.vccio.eq(0b111111)
if hasattr(ddram_pads, "gnd"):
@ -205,7 +204,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

4
litex_boards/targets/pano_logic_g2.py
View File

@ -65,7 +65,6 @@ class BaseSoC(SoCCore):
pads = self.platform.request("eth"),
clk_freq = sys_clk_freq,
with_hw_init_reset = False)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -75,7 +74,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------
@ -85,7 +83,7 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision", default="c", help="Board revision c (default) or b")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")

2
litex_boards/targets/pipistrello.py
View File

@ -178,7 +178,6 @@ class BaseSoC(SoCCore):
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
]
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT46H32M16(sys_clk_freq, "1:2"),
@ -193,7 +192,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/qmtech_ep4ce15.py
View File

@ -89,7 +89,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/qmtech_wukong.py
View File

@ -71,7 +71,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
@ -87,7 +86,6 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -97,7 +95,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/redpitaya.py
View File

@ -86,7 +86,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/sds1104xe.py
View File

@ -80,7 +80,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"),
@ -120,7 +119,6 @@ class BaseSoC(SoCCore):
# Software Interface.
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
self.add_csr("ethmac")
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)

1
litex_boards/targets/simple.py
View File

@ -40,7 +40,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
except:
pass

3
litex_boards/targets/tagus.py
View File

@ -76,7 +76,6 @@ class BaseSoC(SoCCore):
nphases = 4,
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
@ -92,14 +91,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/tec0117.py
View File

@ -120,7 +120,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Flash --------------------------------------------------------------------------------------------

1
litex_boards/targets/tinyfpga_bx.py
View File

@ -61,7 +61,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/trellisboard.py
View File

@ -131,7 +131,6 @@ class BaseSoC(SoCCore):
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"),
@ -147,14 +146,12 @@ class BaseSoC(SoCCore):
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/ulx3s.py
View File

@ -134,17 +134,14 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
def add_oled(self):
pads = self.platform.request("oled_spi")
pads.miso = Signal()
self.submodules.oled_spi = SPIMaster(pads, 8, self.sys_clk_freq, 8e6)
self.oled_spi.add_clk_divider()
self.add_csr("oled_spi")
self.submodules.oled_ctl = GPIOOut(self.platform.request("oled_ctl"))
self.add_csr("oled_ctl")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/vc707.py
View File

@ -66,7 +66,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
@ -82,14 +81,12 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/vcu118.py
View File

@ -73,7 +73,6 @@ class BaseSoC(SoCCore):
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = EDY4016A(sys_clk_freq, "1:4"),
@ -88,7 +87,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

3
litex_boards/targets/versa_ecp5.py
View File

@ -99,7 +99,6 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
@ -119,7 +118,6 @@ class BaseSoC(SoCCore):
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9,
rx_delay = 0e-9)
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
@ -129,7 +127,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

4
litex_boards/targets/xcu1525.py
View File

@ -76,7 +76,6 @@ class BaseSoC(SoCCore):
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT40A512M8(sys_clk_freq, "1:4"),
@ -94,7 +93,6 @@ class BaseSoC(SoCCore):
self.submodules.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_csr("pcie_phy")
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
@ -126,7 +124,6 @@ class BaseSoC(SoCCore):
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
self.add_csr("sata_phy")
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
@ -135,7 +132,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/zcu104.py
View File

@ -74,7 +74,6 @@ class BaseSoC(SoCCore):
memtype = "DDR4",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 500e6)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MTA4ATF51264HZ(sys_clk_freq, "1:4"),
@ -89,7 +88,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

2
litex_boards/targets/ztex213.py
View File

@ -82,7 +82,6 @@ class BaseSoC(SoCCore):
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"), #MT41J128M16XX-125
@ -97,7 +96,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------

1
litex_boards/targets/zybo_z7.py
View File

@ -79,7 +79,6 @@ class BaseSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------