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aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address
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7184032555
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3 changed files with 3 additions and 3 deletions
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@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM):
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.mem_map["csr"])
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lambda a: 1, base_address=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM):
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.mem_map["csr"])
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lambda a: 1, base_address=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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@ -105,7 +105,7 @@ class TagusSoC(SoCSDRAM):
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# pcie wishbone bridge
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self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
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lambda a: 1, shadow_base=self.mem_map["csr"])
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lambda a: 1, base_address=self.mem_map["csr"])
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self.add_wb_master(self.pcie_wishbone.wishbone)
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# pcie dma
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