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aller/nereid/tagus: LitePCIeWishboneBridge's shadow_base replace with base_address

This commit is contained in:
Florent Kermarrec 2019-12-14 22:10:04 +01:00
parent 7184032555
commit 48476be9e2
3 changed files with 3 additions and 3 deletions
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2
litex_boards/partner/targets/aller.py
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@ -103,7 +103,7 @@ class AllerSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.mem_map["csr"]) lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma

2
litex_boards/partner/targets/nereid.py
View File

@ -103,7 +103,7 @@ class NereidSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.mem_map["csr"]) lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma

2
litex_boards/partner/targets/tagus.py
View File

@ -105,7 +105,7 @@ class TagusSoC(SoCSDRAM):
# pcie wishbone bridge # pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint,
lambda a: 1, shadow_base=self.mem_map["csr"]) lambda a: 1, base_address=self.mem_map["csr"])
self.add_wb_master(self.pcie_wishbone.wishbone) self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma # pcie dma