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targets: sync with litex targets

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This commit is contained in:
Florent Kermarrec 2019-09-25 14:07:52 +02:00
parent 0ead12bae8
commit 48cd1208df
7 changed files with 22 additions and 22 deletions
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6
litex_boards/official/targets/genesys2.py
View file

@ -44,10 +44,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
platform = genesys2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
@ -70,7 +70,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))

6
litex_boards/official/targets/kc705.py
View file

@ -46,10 +46,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
platform = kc705.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
@ -72,7 +72,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
self.platform.request("eth"), clk_freq=self.clk_freq)

6
litex_boards/official/targets/kcu105.py
View file

@ -80,10 +80,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
platform = kcu105.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
@ -108,7 +108,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,

6
litex_boards/official/targets/nexys_video.py
View file

@ -49,10 +49,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
platform = nexys_video.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
@ -75,7 +75,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))

8
litex_boards/official/targets/simple.py
View file

@ -19,10 +19,10 @@ from liteeth.mac import LiteEthMAC
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, platform, **kwargs):
def __init__(self, platform, integrated_rom_size=0x8000, **kwargs):
sys_clk_freq = int(1e9/platform.default_clk_period)
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_size=integrated_rom_size,
integrated_main_ram_size=16*1024,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
@ -35,7 +35,7 @@ class EthernetSoC(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, platform, **kwargs):
def __init__(self, platform, integrated_rom_size=0x10000, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
@ -43,7 +43,7 @@ class EthernetSoC(BaseSoC):
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_csr("ethmac")
self.add_interrupt("ethmac")

6
litex_boards/official/targets/versa_ecp5.py
View file

@ -76,10 +76,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_size=integrated_rom_size,
**kwargs)
# crg
@ -107,7 +107,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, toolchain="diamond", **kwargs):
BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"),

6
litex_boards/partner/targets/netv2.py
View file

@ -50,10 +50,10 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
def __init__(self, sys_clk_freq=int(100e6), integrated_rom_size=0x8000, **kwargs):
platform = netv2.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
@ -76,7 +76,7 @@ class EthernetSoC(BaseSoC):
mem_map.update(BaseSoC.mem_map)
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"),
self.platform.request("eth"))