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targets/avnet_aesku40: Fix compilation and minor cleanups.

This commit is contained in:
Florent Kermarrec 2022-06-07 13:08:02 +02:00
parent d37af4aece
commit 4a22f6bf17
1 changed files with 8 additions and 18 deletions
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18
litex_boards/targets/avnet_aesku40.py
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@ -17,16 +17,10 @@ from litex_boards.platforms import avnet_aesku40
from litex.soc.cores.clock import * from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import EDY4016A from litedram.modules import EDY4016A
from litedram.phy import usddrphy from litedram.phy import usddrphy
from liteeth.phy.ku_1000basex import KU_1000BASEX
from litepcie.phy.uspciephy import USPCIEPHY
from litepcie.software import generate_litepcie_software
from liteeth.phy.usrgmii import LiteEthPHYRGMII from liteeth.phy.usrgmii import LiteEthPHYRGMII
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
@ -68,15 +62,12 @@ class BaseSoC(SoCCore):
**kwargs): **kwargs):
platform = avnet_aesku40.Platform() platform = avnet_aesku40.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on AESKU40",
ident_version = True,
**kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AESKU40", **kwargs)
# Ethernet --------------------------------------------------------------------------------- # Ethernet ---------------------------------------------------------------------------------
if with_ethernet: if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII( self.submodules.ethphy = LiteEthPHYRGMII(
@ -85,7 +76,7 @@ class BaseSoC(SoCCore):
tx_delay=1e-9, #Supported Delay with 200 MHz ref clk tx_delay=1e-9, #Supported Delay with 200 MHz ref clk
rx_delay=1e-9) rx_delay=1e-9)
#Change ref clk for idelay3s # Change ref clk for IDELAYE3: FIXME: Allow it direclty in LiteEth?
for special in self.ethphy.rx._fragment.specials: for special in self.ethphy.rx._fragment.specials:
if special.name_override == "IDELAYE3": if special.name_override == "IDELAYE3":
for item in special.items: for item in special.items:
@ -126,7 +117,6 @@ def main():
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)
if args.load: if args.load:
prog = soc.platform.create_programmer() prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))