Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sitlinv_stlv7325: remove unexistent COL/CRS pins 

The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.

Remove these pins from the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng 2022-11-04 10:52:33 +08:00
parent 1c07fa94ca
commit 4ba5793822
1 changed files with 0 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
litex_boards/platforms/sitlinv_stlv7325.py
View File

@ -164,8 +164,6 @@ _io = [
Subsignal("tx_en", Pins("F12")),
Subsignal("tx_er", Pins("E13")),
Subsignal("tx_data", Pins("G12 E11 G11 C14 D14 C13 C11 D13")),
Subsignal("col", Pins("W19")),
Subsignal("crs", Pins("R30")),
IOStandard("LVCMOS15")
),
("eth", 1,
@ -179,8 +177,6 @@ _io = [
Subsignal("tx_en", Pins("F8")),
Subsignal("tx_er", Pins("D9")),
Subsignal("tx_data", Pins("H11 J11 H9 J10 H12 F10 G10 F9")),
Subsignal("col", Pins("W19")),
Subsignal("crs", Pins("R30")),
IOStandard("LVCMOS15")
),