efinix: Avoid no_we on ROM/RAMs (no longer required).
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@ -51,9 +51,6 @@ class BaseSoC(SoCCore):
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SoCCore.__init__(self, platform, sys_clk_freq,
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SoCCore.__init__(self, platform, sys_clk_freq,
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#ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit", # FIXME: Crash design.
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#ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit", # FIXME: Crash design.
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#ident_version = True,
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#ident_version = True,
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integrated_rom_no_we = True, # FIXME: Avoid this.
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integrated_sram_no_we = True, # FIXME: Avoid this.
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integrated_main_ram_no_we = True, # FIXME: Avoid this.
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**kwargs
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**kwargs
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)
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)
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@ -49,9 +49,6 @@ class BaseSoC(SoCCore):
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SoCCore.__init__(self, platform, sys_clk_freq,
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SoCCore.__init__(self, platform, sys_clk_freq,
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#ident = "LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", # FIXME: Crash design.
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#ident = "LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", # FIXME: Crash design.
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#ident_version = True,
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#ident_version = True,
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integrated_rom_no_we = True, # FIXME: Avoid this.
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integrated_sram_no_we = True, # FIXME: Avoid this.
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integrated_main_ram_no_we = True, # FIXME: Avoid this.
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**kwargs
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**kwargs
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)
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)
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@ -60,9 +60,6 @@ class BaseSoC(SoCCore):
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SoCCore.__init__(self, platform, sys_clk_freq,
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SoCCore.__init__(self, platform, sys_clk_freq,
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#ident = "LiteX SoC on Efinix Xyloni Dev Kit", # FIXME: Crash design.
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#ident = "LiteX SoC on Efinix Xyloni Dev Kit", # FIXME: Crash design.
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#ident_version = True,
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#ident_version = True,
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integrated_rom_no_we = True, # FIXME: Avoid this.
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integrated_sram_no_we = True, # FIXME: Avoid this.
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integrated_main_ram_no_we = True, # FIXME: Avoid this.
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**kwargs)
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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