Hardware
/
litex-boards
mirror of https://github.com/litex-hub/litex-boards.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

efinix: Avoid no_we on ROM/RAMs (no longer required).

This commit is contained in:
Florent Kermarrec 2021-10-25 19:10:03 +02:00
parent d13a8d54b8
commit 4bcfde8882
3 changed files with 0 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py
View File

@ -51,9 +51,6 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq,
#ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit", # FIXME: Crash design.
#ident_version = True,
integrated_rom_no_we = True, # FIXME: Avoid this.
integrated_sram_no_we = True, # FIXME: Avoid this.
integrated_main_ram_no_we = True, # FIXME: Avoid this.
**kwargs
)

3
litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
View File

@ -49,9 +49,6 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq,
#ident = "LiteX SoC on Efinix Trion T20 BGA256 Dev Kit", # FIXME: Crash design.
#ident_version = True,
integrated_rom_no_we = True, # FIXME: Avoid this.
integrated_sram_no_we = True, # FIXME: Avoid this.
integrated_main_ram_no_we = True, # FIXME: Avoid this.
**kwargs
)

3
litex_boards/targets/efinix_xyloni_dev_kit.py
View File

@ -60,9 +60,6 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq,
#ident = "LiteX SoC on Efinix Xyloni Dev Kit", # FIXME: Crash design.
#ident_version = True,
integrated_rom_no_we = True, # FIXME: Avoid this.
integrated_sram_no_we = True, # FIXME: Avoid this.
integrated_main_ram_no_we = True, # FIXME: Avoid this.
**kwargs)
# CRG --------------------------------------------------------------------------------------