targets/xilinx_zybo_z7: adding missing variant parameter to the platform
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@ -45,7 +45,7 @@ class _CRG(LiteXModule):
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=100e6, variant="z7-10", with_ps7=False, with_led_chaser=True, **kwargs):
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def __init__(self, sys_clk_freq=100e6, variant="z7-10", with_ps7=False, with_led_chaser=True, **kwargs):
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platform = digilent_zybo_z7.Platform()
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platform = digilent_zybo_z7.Platform(variant=variant)
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self.builder = None
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self.builder = None
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
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use_ps7_clk = (kwargs.get("cpu_type", None) == "zynq7000")
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